Commit 375ee58b authored by Aurelien Jarno's avatar Aurelien Jarno Committed by Alexander Graf
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target-s390x: implement miscellaneous-instruction-extensions facility



RISBGN is the same as RISBG, but without setting the condition code.
CLT and CLGT are the same as CLRT and CLGRT, but using memory for the
second operand.

Reviewed-by: default avatarRichard Henderson <rth@twiddle.net>
Signed-off-by: default avatarAurelien Jarno <aurelien@aurel32.net>
Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
parent df46283c
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+3 −0
Original line number Diff line number Diff line
@@ -230,6 +230,8 @@
/* COMPARE LOGICAL AND TRAP */
    D(0xb973, CLRT,    RRF_c, GIE, r1_32u, r2_32u, 0, 0, ct, 0, 1)
    D(0xb961, CLGRT,   RRF_c, GIE, r1_o, r2_o, 0, 0, ct, 0, 1)
    D(0xeb23, CLT,     RSY_b, MIE, r1_32u, m2_32u, 0, 0, ct, 0, 1)
    D(0xeb2b, CLGT,    RSY_b, MIE, r1_o, m2_64, 0, 0, ct, 0, 1)
    D(0xec73, CLFIT,   RIE_a, GIE, r1_32u, i2_32u, 0, 0, ct, 0, 1)
    D(0xec71, CLGIT,   RIE_a, GIE, r1_o, i2_32u, 0, 0, ct, 0, 1)

@@ -604,6 +606,7 @@

/* ROTATE THEN INSERT SELECTED BITS */
    C(0xec55, RISBG,   RIE_f, GIE, 0, r2, r1, 0, risbg, s64)
    C(0xec59, RISBGN,  RIE_f, MIE, 0, r2, r1, 0, risbg, 0)
    C(0xec5d, RISBHG,  RIE_f, HW,  0, r2, r1, 0, risbg, 0)
    C(0xec51, RISBLG,  RIE_f, HW,  0, r2, r1, 0, risbg, 0)
/* ROTATE_THEN <OP> SELECTED BITS */
+1 −0
Original line number Diff line number Diff line
@@ -1119,6 +1119,7 @@ typedef enum DisasFacility {
    FAC_HFP_MA,             /* HFP multiply-and-add/subtract */
    FAC_HW,                 /* high-word */
    FAC_IEEEE_SIM,          /* IEEE exception sumilation */
    FAC_MIE,                /* miscellaneous-instruction-extensions */
    FAC_LOC,                /* load/store on condition */
    FAC_LD,                 /* long displacement */
    FAC_PC,                 /* population count */