Commit 3716fba3 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging 



virtio, pci: fixes

More fixes missed in the previous pull request.

Signed-off-by: default avatarMichael S. Tsirkin <mst@redhat.com>

# gpg: Signature made Thu 16 Mar 2017 02:29:49 GMT
# gpg:                using RSA key 0x281F0DB8D28D5469
# gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>"
# gpg:                 aka "Michael S. Tsirkin <mst@redhat.com>"
# Primary key fingerprint: 0270 606B 6F3C DF3D 0B17  0970 C350 3912 AFBE 8E67
#      Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA  8A0D 281F 0DB8 D28D 5469

* remotes/mst/tags/for_upstream:
  virtio-serial-bus: Delete timer from list before free it
  hw/virtio: fix Power Management Control Register for PCI Express virtio devices
  hw/virtio: fix Link Control Register for PCI Express virtio devices
  hw/virtio: fix error enabling flags in Device Control register
  hw/pcie: fix Extended Configuration Space for devices with no Extended Capabilities

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 7c756380 bdf4c4ec

dtc @ 65cc4d27

Original line number Diff line number Diff line 
Subproject commit 558cd81bdd432769b59bff01240c44f82cfb1a9d
 
Subproject commit 65cc4d2748a2c2e6f27f1cf39e07a5dbabd80ebf

hw/char/virtio-serial-bus.c

+1 −0
Original line number Diff line number Diff line
@@ -724,6 +724,7 @@ static void virtio_serial_post_load_timer_cb(void *opaque) 
        }

    }

    g_free(s->post_load->connected);

    timer_del(s->post_load->timer);

    timer_free(s->post_load->timer);

    g_free(s->post_load);

    s->post_load = NULL;

hw/pci/pci.c

+2 −0
Original line number Diff line number Diff line
@@ -64,6 +64,8 @@ static Property pci_props[] = { 
                    QEMU_PCI_CAP_SERR_BITNR, true),

    DEFINE_PROP_BIT("x-pcie-lnksta-dllla", PCIDevice, cap_present,

                    QEMU_PCIE_LNKSTA_DLLLA_BITNR, true),

    DEFINE_PROP_BIT("x-pcie-extcap-init", PCIDevice, cap_present,

                    QEMU_PCIE_EXTCAP_INIT_BITNR, true),

    DEFINE_PROP_END_OF_LIST()

};

hw/pci/pcie.c

+20 −0
Original line number Diff line number Diff line
@@ -109,6 +109,12 @@ int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type, uint8_t port) 
                 PCI_EXP_DEVCAP2_EFF | PCI_EXP_DEVCAP2_EETLPP);



    pci_set_word(dev->wmask + pos + PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_EETLPPB);



    if (dev->cap_present & QEMU_PCIE_EXTCAP_INIT) {

        /* read-only to behave like a 'NULL' Extended Capability Header */

        pci_set_long(dev->wmask + PCI_CONFIG_SPACE_SIZE, 0);

    }



    return pos;

}
@@ -217,6 +223,20 @@ void pcie_cap_deverr_reset(PCIDevice *dev) 
                                 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE);

}



void pcie_cap_lnkctl_init(PCIDevice *dev)

{

    uint32_t pos = dev->exp.exp_cap;

    pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_LNKCTL,

                               PCI_EXP_LNKCTL_CCC | PCI_EXP_LNKCTL_ES);

}



void pcie_cap_lnkctl_reset(PCIDevice *dev)

{

    uint8_t *lnkctl = dev->config + dev->exp.exp_cap + PCI_EXP_LNKCTL;

    pci_long_test_and_clear_mask(lnkctl,

                                 PCI_EXP_LNKCTL_CCC | PCI_EXP_LNKCTL_ES);

}



static void hotplug_event_update_event_status(PCIDevice *dev)

{

    uint32_t pos = dev->exp.exp_cap;

hw/virtio/virtio-pci.c

+31 −0
Original line number Diff line number Diff line
@@ -1812,6 +1812,7 @@ static void virtio_pci_realize(PCIDevice *pci_dev, Error **errp) 


        pos = pci_add_capability(pci_dev, PCI_CAP_ID_PM, 0, PCI_PM_SIZEOF);

        assert(pos > 0);

        pci_dev->exp.pm_cap = pos;



        /*

         * Indicates that this function complies with revision 1.2 of the
@@ -1819,6 +1820,22 @@ static void virtio_pci_realize(PCIDevice *pci_dev, Error **errp) 
         */

        pci_set_word(pci_dev->config + pos + PCI_PM_PMC, 0x3);



        if (proxy->flags & VIRTIO_PCI_FLAG_INIT_DEVERR) {

            /* Init error enabling flags */

            pcie_cap_deverr_init(pci_dev);

        }



        if (proxy->flags & VIRTIO_PCI_FLAG_INIT_LNKCTL) {

            /* Init Link Control Register */

            pcie_cap_lnkctl_init(pci_dev);

        }



        if (proxy->flags & VIRTIO_PCI_FLAG_INIT_PM) {

            /* Init Power Management Control Register */

            pci_set_word(pci_dev->wmask + pos + PCI_PM_CTRL,

                         PCI_PM_CTRL_STATE_MASK);

        }



        if (proxy->flags & VIRTIO_PCI_FLAG_ATS) {

            pcie_ats_init(pci_dev, 256);

        }
@@ -1849,6 +1866,7 @@ static void virtio_pci_reset(DeviceState *qdev) 
{

    VirtIOPCIProxy *proxy = VIRTIO_PCI(qdev);

    VirtioBusState *bus = VIRTIO_BUS(&proxy->bus);

    PCIDevice *dev = PCI_DEVICE(qdev);

    int i;



    virtio_pci_stop_ioeventfd(proxy);
@@ -1862,6 +1880,13 @@ static void virtio_pci_reset(DeviceState *qdev) 
        proxy->vqs[i].avail[0] = proxy->vqs[i].avail[1] = 0;

        proxy->vqs[i].used[0] = proxy->vqs[i].used[1] = 0;

    }



    if (pci_is_express(dev)) {

        pcie_cap_deverr_reset(dev);

        pcie_cap_lnkctl_reset(dev);



        pci_set_word(dev->config + dev->exp.pm_cap + PCI_PM_CTRL, 0);

    }

}



static Property virtio_pci_properties[] = {
@@ -1882,6 +1907,12 @@ static Property virtio_pci_properties[] = { 
                     ignore_backend_features, false),

    DEFINE_PROP_BIT("ats", VirtIOPCIProxy, flags,

                    VIRTIO_PCI_FLAG_ATS_BIT, false),

    DEFINE_PROP_BIT("x-pcie-deverr-init", VirtIOPCIProxy, flags,

                    VIRTIO_PCI_FLAG_INIT_DEVERR_BIT, true),

    DEFINE_PROP_BIT("x-pcie-lnkctl-init", VirtIOPCIProxy, flags,

                    VIRTIO_PCI_FLAG_INIT_LNKCTL_BIT, true),

    DEFINE_PROP_BIT("x-pcie-pm-init", VirtIOPCIProxy, flags,

                    VIRTIO_PCI_FLAG_INIT_PM_BIT, true),

    DEFINE_PROP_END_OF_LIST(),

};