Commit 36f48d9c authored by Alexander Graf's avatar Alexander Graf
Browse files

PPC: Depend behavior of cmp instructions only on instruction encoding 



When running an L=1 cmp instruction on a 64bit PPC CPU with SF off, it
still behaves identical to what it does when SF is on. Remove the implicit
difference in the code.

Also, on most 32bit CPUs we should always treat the compare as 32bit
compare, as the CPU will ignore the L bit. This is not true for e500mc,
but that's up for a different patch.

Reported-by: default avatarTorbjorn Granlund <tg@gmplib.org>
Reviewed-by: default avatarRichard Henderson <rth@twiddle.net>
Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
parent 554ecc57

target-ppc/translate.c

+16 −16
Original line number Diff line number Diff line
@@ -675,11 +675,11 @@ static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) 
/* cmp */

static void gen_cmp(DisasContext *ctx)

{

    if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) {

        gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],

    if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {

        gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],

                   1, crfD(ctx->opcode));

    } else {

        gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],

        gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],

                     1, crfD(ctx->opcode));

    }

}
@@ -687,11 +687,11 @@ static void gen_cmp(DisasContext *ctx) 
/* cmpi */

static void gen_cmpi(DisasContext *ctx)

{

    if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) {

        gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),

    if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {

        gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),

                    1, crfD(ctx->opcode));

    } else {

        gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),

        gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),

                      1, crfD(ctx->opcode));

    }

}
@@ -699,11 +699,11 @@ static void gen_cmpi(DisasContext *ctx) 
/* cmpl */

static void gen_cmpl(DisasContext *ctx)

{

    if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) {

        gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],

    if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {

        gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],

                   0, crfD(ctx->opcode));

    } else {

        gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],

        gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],

                     0, crfD(ctx->opcode));

    }

}
@@ -711,11 +711,11 @@ static void gen_cmpl(DisasContext *ctx) 
/* cmpli */

static void gen_cmpli(DisasContext *ctx)

{

    if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) {

        gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),

    if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {

        gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),

                    0, crfD(ctx->opcode));

    } else {

        gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),

        gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),

                      0, crfD(ctx->opcode));

    }

}