Commit 36c6711b authored by Eric Johnson's avatar Eric Johnson Committed by Aurelien Jarno
Browse files

target-mips: allow microMIPS SWP and SDP to have RD equal to BASE 



The microMIPS SWP and SDP instructions do not modify GPRs.  So their
behavior is well defined when RD equals BASE.  The MIPS Architecture
Verification Programs (AVPs) check that they work as expected.  This
is required for AVPs to pass.

Signed-off-by: default avatarEric Johnson <ericj@mips.com>
Signed-off-by: default avatarAurelien Jarno <aurelien@aurel32.net>
parent 2e15497c

target-mips/translate.c

+9 −1
Original line number Diff line number Diff line
@@ -10031,7 +10031,7 @@ static void gen_ldst_pair (DisasContext *ctx, uint32_t opc, int rd, 
    const char *opn = "ldst_pair";

    TCGv t0, t1;



    if (ctx->hflags & MIPS_HFLAG_BMASK || rd == 31 || rd == base) {

    if (ctx->hflags & MIPS_HFLAG_BMASK || rd == 31) {

        generate_exception(ctx, EXCP_RI);

        return;

    }
@@ -10043,6 +10043,10 @@ static void gen_ldst_pair (DisasContext *ctx, uint32_t opc, int rd, 


    switch (opc) {

    case LWP:

        if (rd == base) {

            generate_exception(ctx, EXCP_RI);

            return;

        }

        save_cpu_state(ctx, 0);

        op_ld_lw(t1, t0, ctx);

        gen_store_gpr(t1, rd);
@@ -10064,6 +10068,10 @@ static void gen_ldst_pair (DisasContext *ctx, uint32_t opc, int rd, 
        break;

#ifdef TARGET_MIPS64

    case LDP:

        if (rd == base) {

            generate_exception(ctx, EXCP_RI);

            return;

        }

        save_cpu_state(ctx, 0);

        op_ld_ld(t1, t0, ctx);

        gen_store_gpr(t1, rd);