Commit 36b80ad9 authored by Alistair Francis's avatar Alistair Francis
Browse files

target/riscv: Add the lowRISC Ibex CPU 

Ibex is a small and efficient, 32-bit, in-order RISC-V core with
a 2-stage pipeline that implements the RV32IMC instruction set
architecture.

For more details on lowRISC see here:
https://github.com/lowRISC/ibex



Signed-off-by: default avatarAlistair Francis <alistair.francis@wdc.com>
Reviewed-by: default avatarBin Meng <bin.meng@windriver.com>
Reviewed-by: default avatarLIU Zhiwei <zhiwei_liu@c-sky.com>
parent ff832b77

target/riscv/cpu.c

+10 −0
Original line number Diff line number Diff line
@@ -144,6 +144,15 @@ static void rv32gcsu_priv1_10_0_cpu_init(Object *obj) 
    set_resetvec(env, DEFAULT_RSTVEC);

}



static void rv32imcu_nommu_cpu_init(Object *obj)

{

    CPURISCVState *env = &RISCV_CPU(obj)->env;

    set_misa(env, RV32 | RVI | RVM | RVC | RVU);

    set_priv_version(env, PRIV_VERSION_1_10_0);

    set_resetvec(env, 0x8090);

    qdev_prop_set_bit(DEVICE(obj), "mmu", false);

}



static void rv32imacu_nommu_cpu_init(Object *obj)

{

    CPURISCVState *env = &RISCV_CPU(obj)->env;
@@ -593,6 +602,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { 
    DEFINE_CPU(TYPE_RISCV_CPU_ANY,              riscv_any_cpu_init),

#if defined(TARGET_RISCV32)

    DEFINE_CPU(TYPE_RISCV_CPU_BASE32,           riscv_base32_cpu_init),

    DEFINE_CPU(TYPE_RISCV_CPU_IBEX,             rv32imcu_nommu_cpu_init),

    DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31,       rv32imacu_nommu_cpu_init),

    DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34,       rv32imafcu_nommu_cpu_init),

    DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34,       rv32gcsu_priv1_10_0_cpu_init),

target/riscv/cpu.h

+1 −0
Original line number Diff line number Diff line
@@ -35,6 +35,7 @@ 
#define TYPE_RISCV_CPU_ANY              RISCV_CPU_TYPE_NAME("any")

#define TYPE_RISCV_CPU_BASE32           RISCV_CPU_TYPE_NAME("rv32")

#define TYPE_RISCV_CPU_BASE64           RISCV_CPU_TYPE_NAME("rv64")

#define TYPE_RISCV_CPU_IBEX             RISCV_CPU_TYPE_NAME("lowrisc-ibex")

#define TYPE_RISCV_CPU_SIFIVE_E31       RISCV_CPU_TYPE_NAME("sifive-e31")

#define TYPE_RISCV_CPU_SIFIVE_E34       RISCV_CPU_TYPE_NAME("sifive-e34")

#define TYPE_RISCV_CPU_SIFIVE_E51       RISCV_CPU_TYPE_NAME("sifive-e51")