Commit 35e94905 authored by Richard Henderson's avatar Richard Henderson
Browse files

target-sparc: Introduce gen_check_align 



Tested-by: default avatarMark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: default avatarRichard Henderson <rth@twiddle.net>
parent 3f4288eb

target-sparc/translate.c

+13 −35
Original line number Diff line number Diff line
@@ -1058,6 +1058,13 @@ static void gen_exception(DisasContext *dc, int which) 
    dc->is_br = 1;

}



static void gen_check_align(TCGv addr, int mask)

{

    TCGv_i32 r_mask = tcg_const_i32(mask);

    gen_helper_check_align(cpu_env, addr, r_mask);

    tcg_temp_free_i32(r_mask);

}



static inline void gen_mov_pc_npc(DisasContext *dc)

{

    if (dc->npc == JUMP_PC) {
@@ -4696,8 +4703,6 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) 
#endif

#ifdef TARGET_SPARC64

            } else if (xop == 0x39) { /* V9 return */

                TCGv_i32 r_const;



                save_state(dc);

                cpu_src1 = get_src1(dc, insn);

                cpu_tmp0 = get_temp_tl(dc);
@@ -4715,9 +4720,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) 
                }

                gen_helper_restore(cpu_env);

                gen_mov_pc_npc(dc);

                r_const = tcg_const_i32(3);

                gen_helper_check_align(cpu_env, cpu_tmp0, r_const);

                tcg_temp_free_i32(r_const);

                gen_check_align(cpu_tmp0, 3);

                tcg_gen_mov_tl(cpu_npc, cpu_tmp0);

                dc->npc = DYNAMIC_PC;

                goto jmp_insn;
@@ -4740,16 +4743,12 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) 
                switch (xop) {

                case 0x38:      /* jmpl */

                    {

                        TCGv t;

                        TCGv_i32 r_const;



                        t = gen_dest_gpr(dc, rd);

                        TCGv t = gen_dest_gpr(dc, rd);

                        tcg_gen_movi_tl(t, dc->pc);

                        gen_store_gpr(dc, rd, t);



                        gen_mov_pc_npc(dc);

                        r_const = tcg_const_i32(3);

                        gen_helper_check_align(cpu_env, cpu_tmp0, r_const);

                        tcg_temp_free_i32(r_const);

                        gen_check_align(cpu_tmp0, 3);

                        gen_address_mask(dc, cpu_tmp0);

                        tcg_gen_mov_tl(cpu_npc, cpu_tmp0);

                        dc->npc = DYNAMIC_PC;
@@ -4758,14 +4757,10 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) 
#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)

                case 0x39:      /* rett, V9 return */

                    {

                        TCGv_i32 r_const;



                        if (!supervisor(dc))

                            goto priv_insn;

                        gen_mov_pc_npc(dc);

                        r_const = tcg_const_i32(3);

                        gen_helper_check_align(cpu_env, cpu_tmp0, r_const);

                        tcg_temp_free_i32(r_const);

                        gen_check_align(cpu_tmp0, 3);

                        tcg_gen_mov_tl(cpu_npc, cpu_tmp0);

                        dc->npc = DYNAMIC_PC;

                        gen_helper_rett(cpu_env);
@@ -4861,14 +4856,8 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) 
                    if (rd & 1)

                        goto illegal_insn;

                    else {

                        TCGv_i32 r_const;

                        TCGv_i64 t64;



                        save_state(dc);

                        r_const = tcg_const_i32(7);

                        /* XXX remove alignment check */

                        gen_helper_check_align(cpu_env, cpu_addr, r_const);

                        tcg_temp_free_i32(r_const);

                        gen_address_mask(dc, cpu_addr);

                        t64 = tcg_temp_new_i64();

                        tcg_gen_qemu_ld64(t64, cpu_addr, dc->mem_idx);
@@ -5079,18 +5068,11 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) 
                    if (rd & 1)

                        goto illegal_insn;

                    else {

                        TCGv_i32 r_const;

                        TCGv_i64 t64;

                        TCGv lo;



                        save_state(dc);

                        gen_address_mask(dc, cpu_addr);

                        r_const = tcg_const_i32(7);

                        /* XXX remove alignment check */

                        gen_helper_check_align(cpu_env, cpu_addr, r_const);

                        tcg_temp_free_i32(r_const);

                        lo = gen_load_gpr(dc, rd + 1);



                        t64 = tcg_temp_new_i64();

                        tcg_gen_concat_tl_i64(t64, lo, cpu_val);

                        tcg_gen_qemu_st64(t64, cpu_addr, dc->mem_idx);
@@ -5203,15 +5185,11 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) 
                    break;

                case 0x36: /* V9 stqfa */

                    {

                        TCGv_i32 r_const;



                        CHECK_FPU_FEATURE(dc, FLOAT128);

                        if (gen_trap_ifnofpu(dc)) {

                            goto jmp_insn;

                        }

                        r_const = tcg_const_i32(7);

                        gen_helper_check_align(cpu_env, cpu_addr, r_const);

                        tcg_temp_free_i32(r_const);

                        gen_check_align(cpu_addr, 7);

                        gen_stf_asi(dc, cpu_addr, insn, 16, QFPREG(rd));

                    }

                    break;