Commit 35cdaad6 authored by Jocelyn Mayer's avatar Jocelyn Mayer
Browse files

Code provision for new PowerPC embedded target support with: 

- 1 kB page size
- 64 bits GPR
- 64 bits physical address space
- SPE extension support.
Change TARGET_PPCSPE into TARGET_PPCEMB


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2718 c046a42c-6fe2-441c-8c8c-71466251a162
parent c294fc58

target-ppc/cpu.h

+8 −3
Original line number Diff line number Diff line
@@ -23,11 +23,13 @@ 
#include "config.h"

#include <inttypes.h>



#if !defined(TARGET_PPCEMB)

#if defined(TARGET_PPC64) || (HOST_LONG_BITS >= 64)

/* When using 64 bits temporary registers,

 * we can use 64 bits GPR with no extra cost

 */

#define TARGET_PPCSPE

#define TARGET_PPCEMB

#endif

#endif



#if defined (TARGET_PPC64)
@@ -35,7 +37,8 @@ typedef uint64_t ppc_gpr_t; 
#define TARGET_LONG_BITS 64

#define TARGET_GPR_BITS  64

#define REGX "%016" PRIx64

#elif defined(TARGET_PPCSPE)

#define TARGET_PAGE_BITS 12

#elif defined(TARGET_PPCEMB)

/* e500v2 have 36 bits physical address space */

#define TARGET_PHYS_ADDR_BITS 64

/* GPR are 64 bits: used by vector extension */
@@ -43,11 +46,14 @@ typedef uint64_t ppc_gpr_t; 
#define TARGET_LONG_BITS 32

#define TARGET_GPR_BITS  64

#define REGX "%016" PRIx64

/* Pages can be 1 kB small */

#define TARGET_PAGE_BITS 10

#else

typedef uint32_t ppc_gpr_t;

#define TARGET_LONG_BITS 32

#define TARGET_GPR_BITS  32

#define REGX "%08" PRIx32

#define TARGET_PAGE_BITS 12

#endif



#include "cpu-defs.h"
@@ -893,7 +899,6 @@ int ppcemb_tlb_search (CPUPPCState *env, target_ulong address); 
int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp);

int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val);



#define TARGET_PAGE_BITS 12

#include "cpu-all.h"



/*****************************************************************************/

target-ppc/exec.h

+1 −1
Original line number Diff line number Diff line
@@ -43,7 +43,7 @@ register unsigned long T1 asm(AREG2); 
register unsigned long T2 asm(AREG3);

#endif

/* We may, sometime, need 64 bits registers on 32 bits target */

#if defined(TARGET_PPC64) || defined(TARGET_PPCSPE) || (HOST_LONG_BITS == 64)

#if defined(TARGET_PPC64) || defined(TARGET_PPCEMB) || (HOST_LONG_BITS == 64)

#define T0_64 T0

#define T1_64 T1

#define T2_64 T2

target-ppc/op.c

+2 −2
Original line number Diff line number Diff line
@@ -2479,7 +2479,7 @@ void OPPROTO op_store_booke_tsr (void) 


#endif /* !defined(CONFIG_USER_ONLY) */



#if defined(TARGET_PPCSPE)

#if defined(TARGET_PPCEMB)

/* SPE extension */

void OPPROTO op_splatw_T1_64 (void)

{
@@ -3198,4 +3198,4 @@ void OPPROTO op_efdtsteq (void) 
    T0 = _do_efdtsteq(T0_64, T1_64);

    RETURN();

}

#endif /* defined(TARGET_PPCSPE) */
 
#endif /* defined(TARGET_PPCEMB) */

target-ppc/op_helper.c

+2 −2
Original line number Diff line number Diff line
@@ -1340,7 +1340,7 @@ void do_440_dlmzb (void) 
    T0 = i;

}



#if defined(TARGET_PPCSPE)

#if defined(TARGET_PPCEMB)

/* SPE extension helpers */

/* Use a table to make this quicker */

static uint8_t hbrev[16] = {
@@ -2200,7 +2200,7 @@ DO_SPE_OP1(fsctuiz); 
DO_SPE_OP1(fsctsf);

/* evfsctuf */

DO_SPE_OP1(fsctuf);

#endif /* defined(TARGET_PPCSPE) */

#endif /* defined(TARGET_PPCEMB) */



/*****************************************************************************/

/* Softmmu support */

target-ppc/op_helper.h

+4 −4
Original line number Diff line number Diff line
@@ -183,7 +183,7 @@ void do_load_403_pb (int num); 
void do_store_403_pb (int num);

#endif



#if defined(TARGET_PPCSPE)

#if defined(TARGET_PPCEMB)

/* SPE extension helpers */

void do_brinc (void);

/* Fixed-point vector helpers */
@@ -264,7 +264,7 @@ void do_evfsctsi (void); 
void do_evfsctui (void);

void do_evfsctsiz (void);

void do_evfsctuiz (void);

#endif /* defined(TARGET_PPCSPE) */

#endif /* defined(TARGET_PPCEMB) */



/* Inlined helpers: used in micro-operation as well as helpers */

/* Generic fixed-point helpers */
@@ -338,7 +338,7 @@ static inline int _do_cntlzd (uint64_t val) 
    return cnt;

}



#if defined(TARGET_PPCSPE)

#if defined(TARGET_PPCEMB)

/* SPE extension */

/* Single precision floating-point helpers */

static inline uint32_t _do_efsabs (uint32_t val)
@@ -459,5 +459,5 @@ static inline int _do_efdtsteq (uint64_t op1, uint64_t op2) 
    u2.u = op2;

    return float64_eq(u1.f, u2.f, &env->spe_status) ? 1 : 0;

}

#endif /* defined(TARGET_PPCSPE) */

#endif /* defined(TARGET_PPCEMB) */

#endif