Commit 352367e8 authored by Sebastian Macke's avatar Sebastian Macke Committed by Jia Liu
Browse files

target-openrisc: Speed up move instruction 



The OpenRISC architecture does not have its own move register
instruction. Instead it uses either "l.addi rd, r0, x" or
"l.ori rd, rs, 0" or "l.or rd, rx, r0"

The l.ori instruction is automatically optimized but not the l.addi instruction.
This patch optimizes for this special case.

Signed-off-by: default avatarSebastian Macke <sebastian@macke.de>
Reviewed-by: default avatarJia Liu <proljc@gmail.com>
Signed-off-by: default avatarJia Liu <proljc@gmail.com>
parent 394cfa39

target-openrisc/translate.c

+27 −23
Original line number Diff line number Diff line
@@ -904,6 +904,9 @@ static void dec_misc(DisasContext *dc, uint32_t insn) 
    case 0x27:    /* l.addi */

        LOG_DIS("l.addi r%d, r%d, %d\n", rd, ra, I16);

        {

            if (I16 == 0) {

                tcg_gen_mov_tl(cpu_R[rd], cpu_R[ra]);

            } else {

                int lab = gen_new_label();

                TCGv_i64 ta = tcg_temp_new_i64();

                TCGv_i64 td = tcg_temp_local_new_i64();
@@ -928,6 +931,7 @@ static void dec_misc(DisasContext *dc, uint32_t insn) 
                tcg_temp_free_i32(res);

                tcg_temp_free_i32(sr_ove);

            }

        }

        break;



    case 0x28:    /* l.addic */