Commit 346fe0c4 authored by Anthony Liguori's avatar Anthony Liguori
Browse files

Merge remote-tracking branch 'stefanha/trivial-patches' into staging 

* stefanha/trivial-patches:
  target-arm: Fix typos in comments
  arm: translate: comment typo - s/middel/middle/
  vl.c: Exit QEMU early if no machine is found
parents 53810bab b90372ad

target-arm/arm-semi.c

+1 −1
Original line number Diff line number Diff line
@@ -281,7 +281,7 @@ uint32_t do_arm_semihosting(CPUARMState *env) 
            return len - ret;

        }

    case TARGET_SYS_READC:

       /* XXX: Read from debug cosole. Not implemented.  */

       /* XXX: Read from debug console. Not implemented.  */

        return 0;

    case TARGET_SYS_ISTTY:

        if (use_gdb_syscalls()) {

target-arm/cpu.h

+1 −1
Original line number Diff line number Diff line
@@ -79,7 +79,7 @@ struct arm_boot_info; 
typedef struct CPUARMState {

    /* Regs for current mode.  */

    uint32_t regs[16];

    /* Frequently accessed CPSR bits are stored separately for efficiently.

    /* Frequently accessed CPSR bits are stored separately for efficiency.

       This contains all the other bits.  Use cpsr_{read,write} to access

       the whole CPSR.  */

    uint32_t uncached_cpsr;

target-arm/helper.c

+3 −3
Original line number Diff line number Diff line
@@ -988,7 +988,7 @@ static void ttbr164_reset(CPUARMState *env, const ARMCPRegInfo *ri) 
}



static const ARMCPRegInfo lpae_cp_reginfo[] = {

    /* NOP AMAIR0/1: the override is because these clash with tha rather

    /* NOP AMAIR0/1: the override is because these clash with the rather

     * broadly specified TLB_LOCKDOWN entry in the generic cp_reginfo.

     */

    { .name = "AMAIR0", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
@@ -2899,8 +2899,8 @@ uint32_t HELPER(logicq_cc)(uint64_t val) 
    return (val >> 32) | (val != 0);

}



/* VFP support.  We follow the convention used for VFP instrunctions:

   Single precition routines have a "s" suffix, double precision a

/* VFP support.  We follow the convention used for VFP instructions:

   Single precision routines have a "s" suffix, double precision a

   "d" suffix.  */



/* Convert host exception flags to vfp form.  */

target-arm/neon_helper.c

+13 −13
Original line number Diff line number Diff line
@@ -530,7 +530,7 @@ NEON_VOP(rshl_s16, neon_s16, 2) 
#undef NEON_FN



/* The addition of the rounding constant may overflow, so we use an

 * intermediate 64 bits accumulator.  */

 * intermediate 64 bit accumulator.  */

uint32_t HELPER(neon_rshl_s32)(uint32_t valop, uint32_t shiftop)

{

    int32_t dest;
@@ -547,8 +547,8 @@ uint32_t HELPER(neon_rshl_s32)(uint32_t valop, uint32_t shiftop) 
    return dest;

}



/* Handling addition overflow with 64 bits inputs values is more

 * tricky than with 32 bits values.  */

/* Handling addition overflow with 64 bit input values is more

 * tricky than with 32 bit values.  */

uint64_t HELPER(neon_rshl_s64)(uint64_t valop, uint64_t shiftop)

{

    int8_t shift = (int8_t)shiftop;
@@ -590,7 +590,7 @@ NEON_VOP(rshl_u16, neon_u16, 2) 
#undef NEON_FN



/* The addition of the rounding constant may overflow, so we use an

 * intermediate 64 bits accumulator.  */

 * intermediate 64 bit accumulator.  */

uint32_t HELPER(neon_rshl_u32)(uint32_t val, uint32_t shiftop)

{

    uint32_t dest;
@@ -608,8 +608,8 @@ uint32_t HELPER(neon_rshl_u32)(uint32_t val, uint32_t shiftop) 
    return dest;

}



/* Handling addition overflow with 64 bits inputs values is more

 * tricky than with 32 bits values.  */

/* Handling addition overflow with 64 bit input values is more

 * tricky than with 32 bit values.  */

uint64_t HELPER(neon_rshl_u64)(uint64_t val, uint64_t shiftop)

{

    int8_t shift = (uint8_t)shiftop;
@@ -817,7 +817,7 @@ NEON_VOP_ENV(qrshl_u16, neon_u16, 2) 
#undef NEON_FN



/* The addition of the rounding constant may overflow, so we use an

 * intermediate 64 bits accumulator.  */

 * intermediate 64 bit accumulator.  */

uint32_t HELPER(neon_qrshl_u32)(CPUARMState *env, uint32_t val, uint32_t shiftop)

{

    uint32_t dest;
@@ -846,8 +846,8 @@ uint32_t HELPER(neon_qrshl_u32)(CPUARMState *env, uint32_t val, uint32_t shiftop 
    return dest;

}



/* Handling addition overflow with 64 bits inputs values is more

 * tricky than with 32 bits values.  */

/* Handling addition overflow with 64 bit input values is more

 * tricky than with 32 bit values.  */

uint64_t HELPER(neon_qrshl_u64)(CPUARMState *env, uint64_t val, uint64_t shiftop)

{

    int8_t shift = (int8_t)shiftop;
@@ -914,7 +914,7 @@ NEON_VOP_ENV(qrshl_s16, neon_s16, 2) 
#undef NEON_FN



/* The addition of the rounding constant may overflow, so we use an

 * intermediate 64 bits accumulator.  */

 * intermediate 64 bit accumulator.  */

uint32_t HELPER(neon_qrshl_s32)(CPUARMState *env, uint32_t valop, uint32_t shiftop)

{

    int32_t dest;
@@ -942,8 +942,8 @@ uint32_t HELPER(neon_qrshl_s32)(CPUARMState *env, uint32_t valop, uint32_t shift 
    return dest;

}



/* Handling addition overflow with 64 bits inputs values is more

 * tricky than with 32 bits values.  */

/* Handling addition overflow with 64 bit input values is more

 * tricky than with 32 bit values.  */

uint64_t HELPER(neon_qrshl_s64)(CPUARMState *env, uint64_t valop, uint64_t shiftop)

{

    int8_t shift = (uint8_t)shiftop;
@@ -1671,7 +1671,7 @@ uint64_t HELPER(neon_negl_u64)(uint64_t x) 
    return -x;

}



/* Saturnating sign manuipulation.  */

/* Saturating sign manipulation.  */

/* ??? Make these use NEON_VOP1 */

#define DO_QABS8(x) do { \

    if (x == (int8_t)0x80) { \

target-arm/op_helper.c

+1 −1
Original line number Diff line number Diff line
@@ -99,7 +99,7 @@ void tlb_fill(CPUARMState *env1, target_ulong addr, int is_write, int mmu_idx, 
}

#endif



/* FIXME: Pass an axplicit pointer to QF to CPUARMState, and move saturating

/* FIXME: Pass an explicit pointer to QF to CPUARMState, and move saturating

   instructions into helper.c  */

uint32_t HELPER(add_setq)(uint32_t a, uint32_t b)

{