Unverified Commit 3390537b authored by Artyom Tarasenko's avatar Artyom Tarasenko
Browse files

target-sparc: add ST_BLKINIT_ ASIs for UA2005+ CPUs 



In OpenSPARC T1+ TWINX ASIs in store instructions are aliased
with Block Initializing Store ASIs.

"UltraSPARC T1 Supplement Draft D2.1, 14 May 2007" describes them
in the chapter "5.9 Block Initializing Store ASIs"

Integer stores of all sizes are allowed with these ASIs.

Signed-off-by: default avatarArtyom Tarasenko <atar4qemu@gmail.com>
parent 7285fba0

target/sparc/translate.c

+11 −0
Original line number Diff line number Diff line
@@ -2321,8 +2321,19 @@ static void gen_st_asi(DisasContext *dc, TCGv src, TCGv addr, 
    case GET_ASI_EXCP:

        break;

    case GET_ASI_DTWINX: /* Reserved for stda.  */

#ifndef TARGET_SPARC64

        gen_exception(dc, TT_ILL_INSN);

        break;

#else

        if (!(dc->def->features & CPU_FEATURE_HYPV)) {

            /* Pre OpenSPARC CPUs don't have these */

            gen_exception(dc, TT_ILL_INSN);

            return;

        }

        /* in OpenSPARC T1+ CPUs TWINX ASIs in store instructions

         * are ST_BLKINIT_ ASIs */

        /* fall through */

#endif

    case GET_ASI_DIRECT:

        gen_address_mask(dc, addr);

        tcg_gen_qemu_st_tl(src, addr, da.mem_idx, da.memop);