Commit 31e6d704 authored by Anup Patel's avatar Anup Patel Committed by Alistair Francis
Browse files

hw/riscv/spike: Allow more than one CPUs 



Currently, the upstream Spike ISA simulator allows more than
one CPUs so we update QEMU Spike machine on similar lines to
allow more than one CPUs.

The maximum number of CPUs for QEMU Spike machine is kept
same as QEMU Virt machine.

Signed-off-by: default avatarAnup Patel <anup.patel@wdc.com>
Reviewed-by: default avatarAlistair Francis <alistair.francis@wdc.com>
Message-id: 20200427080644.168461-4-anup.patel@wdc.com
Message-Id: <20200427080644.168461-4-anup.patel@wdc.com>
Signed-off-by: default avatarAlistair Francis <alistair.francis@wdc.com>
parent 5b8a9863

hw/riscv/spike.c

+1 −1
Original line number Diff line number Diff line
@@ -476,7 +476,7 @@ static void spike_machine_init(MachineClass *mc) 
{

    mc->desc = "RISC-V Spike Board";

    mc->init = spike_board_init;

    mc->max_cpus = 1;

    mc->max_cpus = 8;

    mc->is_default = true;

    mc->default_cpu_type = SPIKE_V1_10_0_CPU;

}