Commit 31bf42a2 authored by LIU Zhiwei's avatar LIU Zhiwei Committed by Alistair Francis
Browse files

target/riscv: vector compress instruction 



Signed-off-by: default avatarLIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Message-Id: <20200701152549.1218-61-zhiwei_liu@c-sky.com>
Signed-off-by: default avatarAlistair Francis <alistair.francis@wdc.com>
parent e4b83d5c

target/riscv/helper.h

+5 −0
Original line number Diff line number Diff line
@@ -1145,3 +1145,8 @@ DEF_HELPER_6(vrgather_vx_b, void, ptr, ptr, tl, ptr, env, i32) 
DEF_HELPER_6(vrgather_vx_h, void, ptr, ptr, tl, ptr, env, i32)

DEF_HELPER_6(vrgather_vx_w, void, ptr, ptr, tl, ptr, env, i32)

DEF_HELPER_6(vrgather_vx_d, void, ptr, ptr, tl, ptr, env, i32)



DEF_HELPER_6(vcompress_vm_b, void, ptr, ptr, ptr, ptr, env, i32)

DEF_HELPER_6(vcompress_vm_h, void, ptr, ptr, ptr, ptr, env, i32)

DEF_HELPER_6(vcompress_vm_w, void, ptr, ptr, ptr, ptr, env, i32)

DEF_HELPER_6(vcompress_vm_d, void, ptr, ptr, ptr, ptr, env, i32)

target/riscv/insn32.decode

+1 −0
Original line number Diff line number Diff line
@@ -577,6 +577,7 @@ vslide1down_vx 001111 . ..... ..... 110 ..... 1010111 @r_vm 
vrgather_vv     001100 . ..... ..... 000 ..... 1010111 @r_vm

vrgather_vx     001100 . ..... ..... 100 ..... 1010111 @r_vm

vrgather_vi     001100 . ..... ..... 011 ..... 1010111 @r_vm

vcompress_vm    010111 - ..... ..... 010 ..... 1010111 @r



vsetvli         0 ........... ..... 111 ..... 1010111  @r2_zimm

vsetvl          1000000 ..... ..... 111 ..... 1010111  @r

target/riscv/insn_trans/trans_rvv.inc.c

+32 −0
Original line number Diff line number Diff line
@@ -2854,3 +2854,35 @@ static bool trans_vrgather_vi(DisasContext *s, arg_rmrr *a) 
    }

    return true;

}



/* Vector Compress Instruction */

static bool vcompress_vm_check(DisasContext *s, arg_r *a)

{

    return (vext_check_isa_ill(s) &&

            vext_check_reg(s, a->rd, false) &&

            vext_check_reg(s, a->rs2, false) &&

            vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs1, 1) &&

            (a->rd != a->rs2));

}



static bool trans_vcompress_vm(DisasContext *s, arg_r *a)

{

    if (vcompress_vm_check(s, a)) {

        uint32_t data = 0;

        static gen_helper_gvec_4_ptr * const fns[4] = {

            gen_helper_vcompress_vm_b, gen_helper_vcompress_vm_h,

            gen_helper_vcompress_vm_w, gen_helper_vcompress_vm_d,

        };

        TCGLabel *over = gen_new_label();

        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);



        data = FIELD_DP32(data, VDATA, MLEN, s->mlen);

        data = FIELD_DP32(data, VDATA, LMUL, s->lmul);

        tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),

                           vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),

                           cpu_env, 0, s->vlen / 8, data, fns[s->sew]);

        gen_set_label(over);

        return true;

    }

    return false;

}

target/riscv/vector_helper.c

+26 −0
Original line number Diff line number Diff line
@@ -4871,3 +4871,29 @@ GEN_VEXT_VRGATHER_VX(vrgather_vx_b, uint8_t, H1, clearb) 
GEN_VEXT_VRGATHER_VX(vrgather_vx_h, uint16_t, H2, clearh)

GEN_VEXT_VRGATHER_VX(vrgather_vx_w, uint32_t, H4, clearl)

GEN_VEXT_VRGATHER_VX(vrgather_vx_d, uint64_t, H8, clearq)



/* Vector Compress Instruction */

#define GEN_VEXT_VCOMPRESS_VM(NAME, ETYPE, H, CLEAR_FN)                   \

void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,               \

                  CPURISCVState *env, uint32_t desc)                      \

{                                                                         \

    uint32_t mlen = vext_mlen(desc);                                      \

    uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen;                   \

    uint32_t vl = env->vl;                                                \

    uint32_t num = 0, i;                                                  \

                                                                          \

    for (i = 0; i < vl; i++) {                                            \

        if (!vext_elem_mask(vs1, mlen, i)) {                              \

            continue;                                                     \

        }                                                                 \

        *((ETYPE *)vd + H(num)) = *((ETYPE *)vs2 + H(i));                 \

        num++;                                                            \

    }                                                                     \

    CLEAR_FN(vd, num, num * sizeof(ETYPE), vlmax * sizeof(ETYPE));        \

}



/* Compress into vd elements of vs2 where vs1 is enabled */

GEN_VEXT_VCOMPRESS_VM(vcompress_vm_b, uint8_t, H1, clearb)

GEN_VEXT_VCOMPRESS_VM(vcompress_vm_h, uint16_t, H2, clearh)

GEN_VEXT_VCOMPRESS_VM(vcompress_vm_w, uint32_t, H4, clearl)

GEN_VEXT_VCOMPRESS_VM(vcompress_vm_d, uint64_t, H8, clearq)