Unverified Commit 30efbf33 authored by Fabien Chouteau's avatar Fabien Chouteau Committed by Palmer Dabbelt
Browse files

SiFive RISC-V GPIO Device 



QEMU model of the GPIO device on the SiFive E300 series SOCs.

The pins are not used by a board definition yet, however this
implementation can already be used to trigger GPIO interrupts from the
software by configuring a pin as both output and input.

Signed-off-by: default avatarFabien Chouteau <chouteau@adacore.com>
Reviewed-by: default avatarPalmer Dabbelt <palmer@sifive.com>
Signed-off-by: default avatarPalmer Dabbelt <palmer@sifive.com>
parent a7b21f67

Makefile.objs

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@@ -182,6 +182,7 @@ trace-events-subdirs += hw/virtio 
trace-events-subdirs += hw/watchdog

trace-events-subdirs += hw/xen

trace-events-subdirs += hw/gpio

trace-events-subdirs += hw/riscv

trace-events-subdirs += migration

trace-events-subdirs += net

trace-events-subdirs += ui

hw/riscv/Makefile.objs

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@@ -2,6 +2,7 @@ obj-$(CONFIG_SPIKE) += riscv_htif.o 
obj-$(CONFIG_HART) += riscv_hart.o

obj-$(CONFIG_SIFIVE_E) += sifive_e.o

obj-$(CONFIG_SIFIVE) += sifive_clint.o

obj-$(CONFIG_SIFIVE) += sifive_gpio.o

obj-$(CONFIG_SIFIVE) += sifive_prci.o

obj-$(CONFIG_SIFIVE) += sifive_plic.o

obj-$(CONFIG_SIFIVE) += sifive_test.o

hw/riscv/sifive_e.c

+26 −2
Original line number Diff line number Diff line
@@ -146,11 +146,15 @@ static void riscv_sifive_e_soc_init(Object *obj) 
                            &error_abort);

    object_property_set_int(OBJECT(&s->cpus), smp_cpus, "num-harts",

                            &error_abort);

    sysbus_init_child_obj(obj, "riscv.sifive.e.gpio0",

                          &s->gpio, sizeof(s->gpio),

                          TYPE_SIFIVE_GPIO);

}



static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp)

{

    const struct MemmapEntry *memmap = sifive_e_memmap;

    Error *err = NULL;



    SiFiveESoCState *s = RISCV_E_SOC(dev);

    MemoryRegion *sys_mem = get_system_memory();
@@ -184,8 +188,28 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp) 
    sifive_mmio_emulate(sys_mem, "riscv.sifive.e.aon",

        memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size);

    sifive_prci_create(memmap[SIFIVE_E_PRCI].base);

    sifive_mmio_emulate(sys_mem, "riscv.sifive.e.gpio0",

        memmap[SIFIVE_E_GPIO0].base, memmap[SIFIVE_E_GPIO0].size);



    /* GPIO */



    object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err);

    if (err) {

        error_propagate(errp, err);

        return;

    }



    /* Map GPIO registers */

    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_E_GPIO0].base);



    /* Pass all GPIOs to the SOC layer so they are available to the board */

    qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL);



    /* Connect GPIO interrupts to the PLIC */

    for (int i = 0; i < 32; i++) {

        sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i,

                           qdev_get_gpio_in(DEVICE(s->plic),

                                            SIFIVE_E_GPIO0_IRQ0 + i));

    }



    sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART0].base,

        serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART0_IRQ));

    sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi0",

hw/riscv/sifive_gpio.c

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Original line number Diff line number Diff line 
/*

 * sifive System-on-Chip general purpose input/output register definition

 *

 * Copyright 2019 AdaCore

 *

 * Base on nrf51_gpio.c:

 *

 * Copyright 2018 Steffen Görtz <contrib@steffen-goertz.de>

 *

 * This code is licensed under the GPL version 2 or later.  See

 * the COPYING file in the top-level directory.

 */



#include "qemu/osdep.h"

#include "qemu/log.h"

#include "hw/riscv/sifive_gpio.h"

#include "trace.h"



static void update_output_irq(SIFIVEGPIOState *s)

{



    uint32_t pending;

    uint32_t pin;



    pending = s->high_ip & s->high_ie;

    pending |= s->low_ip & s->low_ie;

    pending |= s->rise_ip & s->rise_ie;

    pending |= s->fall_ip & s->fall_ie;



    for (int i = 0; i < SIFIVE_GPIO_PINS; i++) {

        pin = 1 << i;

        qemu_set_irq(s->irq[i], (pending & pin) != 0);

        trace_sifive_gpio_update_output_irq(i, (pending & pin) != 0);

    }

}



static void update_state(SIFIVEGPIOState *s)

{

    size_t i;

    bool prev_ival, in, in_mask, port, out_xor, pull, output_en, input_en,

        rise_ip, fall_ip, low_ip, high_ip, oval, actual_value, ival;



    for (i = 0; i < SIFIVE_GPIO_PINS; i++) {



        prev_ival = extract32(s->value, i, 1);

        in        = extract32(s->in, i, 1);

        in_mask   = extract32(s->in_mask, i, 1);

        port      = extract32(s->port, i, 1);

        out_xor   = extract32(s->out_xor, i, 1);

        pull      = extract32(s->pue, i, 1);

        output_en = extract32(s->output_en, i, 1);

        input_en  = extract32(s->input_en, i, 1);

        rise_ip   = extract32(s->rise_ip, i, 1);

        fall_ip   = extract32(s->fall_ip, i, 1);

        low_ip    = extract32(s->low_ip, i, 1);

        high_ip   = extract32(s->high_ip, i, 1);



        /* Output value (IOF not supported) */

        oval = output_en && (port ^ out_xor);



        /* Pin both driven externally and internally */

        if (output_en && in_mask) {

            qemu_log_mask(LOG_GUEST_ERROR, "GPIO pin %zu short circuited\n", i);

        }



        if (in_mask) {

            /* The pin is driven by external device */

            actual_value = in;

        } else if (output_en) {

            /* The pin is driven by internal circuit */

            actual_value = oval;

        } else {

            /* Floating? Apply pull-up resistor */

            actual_value = pull;

        }



        qemu_set_irq(s->output[i], actual_value);



        /* Input value */

        ival = input_en && actual_value;



        /* Interrupts */

        high_ip = high_ip || ival;

        s->high_ip = deposit32(s->high_ip, i, 1, high_ip);



        low_ip = low_ip || !ival;

        s->low_ip = deposit32(s->low_ip,  i, 1, low_ip);



        rise_ip = rise_ip || (ival && !prev_ival);

        s->rise_ip = deposit32(s->rise_ip, i, 1, rise_ip);



        fall_ip = fall_ip || (!ival && prev_ival);

        s->fall_ip = deposit32(s->fall_ip, i, 1, fall_ip);



        /* Update value */

        s->value = deposit32(s->value, i, 1, ival);

    }

    update_output_irq(s);

}



static uint64_t sifive_gpio_read(void *opaque, hwaddr offset, unsigned int size)

{

    SIFIVEGPIOState *s = SIFIVE_GPIO(opaque);

    uint64_t r = 0;



    switch (offset) {

    case SIFIVE_GPIO_REG_VALUE:

        r = s->value;

        break;



    case SIFIVE_GPIO_REG_INPUT_EN:

        r = s->input_en;

        break;



    case SIFIVE_GPIO_REG_OUTPUT_EN:

        r = s->output_en;

        break;



    case SIFIVE_GPIO_REG_PORT:

        r = s->port;

        break;



    case SIFIVE_GPIO_REG_PUE:

        r = s->pue;

        break;



    case SIFIVE_GPIO_REG_DS:

        r = s->ds;

        break;



    case SIFIVE_GPIO_REG_RISE_IE:

        r = s->rise_ie;

        break;



    case SIFIVE_GPIO_REG_RISE_IP:

        r = s->rise_ip;

        break;



    case SIFIVE_GPIO_REG_FALL_IE:

        r = s->fall_ie;

        break;



    case SIFIVE_GPIO_REG_FALL_IP:

        r = s->fall_ip;

        break;



    case SIFIVE_GPIO_REG_HIGH_IE:

        r = s->high_ie;

        break;



    case SIFIVE_GPIO_REG_HIGH_IP:

        r = s->high_ip;

        break;



    case SIFIVE_GPIO_REG_LOW_IE:

        r = s->low_ie;

        break;



    case SIFIVE_GPIO_REG_LOW_IP:

        r = s->low_ip;

        break;



    case SIFIVE_GPIO_REG_IOF_EN:

        r = s->iof_en;

        break;



    case SIFIVE_GPIO_REG_IOF_SEL:

        r = s->iof_sel;

        break;



    case SIFIVE_GPIO_REG_OUT_XOR:

        r = s->out_xor;

        break;



    default:

        qemu_log_mask(LOG_GUEST_ERROR,

                "%s: bad read offset 0x%" HWADDR_PRIx "\n",

                      __func__, offset);

    }



    trace_sifive_gpio_read(offset, r);



    return r;

}



static void sifive_gpio_write(void *opaque, hwaddr offset,

                       uint64_t value, unsigned int size)

{

    SIFIVEGPIOState *s = SIFIVE_GPIO(opaque);



    trace_sifive_gpio_write(offset, value);



    switch (offset) {



    case SIFIVE_GPIO_REG_INPUT_EN:

        s->input_en = value;

        break;



    case SIFIVE_GPIO_REG_OUTPUT_EN:

        s->output_en = value;

        break;



    case SIFIVE_GPIO_REG_PORT:

        s->port = value;

        break;



    case SIFIVE_GPIO_REG_PUE:

        s->pue = value;

        break;



    case SIFIVE_GPIO_REG_DS:

        s->ds = value;

        break;



    case SIFIVE_GPIO_REG_RISE_IE:

        s->rise_ie = value;

        break;



    case SIFIVE_GPIO_REG_RISE_IP:

         /* Write 1 to clear */

        s->rise_ip &= ~value;

        break;



    case SIFIVE_GPIO_REG_FALL_IE:

        s->fall_ie = value;

        break;



    case SIFIVE_GPIO_REG_FALL_IP:

         /* Write 1 to clear */

        s->fall_ip &= ~value;

        break;



    case SIFIVE_GPIO_REG_HIGH_IE:

        s->high_ie = value;

        break;



    case SIFIVE_GPIO_REG_HIGH_IP:

         /* Write 1 to clear */

        s->high_ip &= ~value;

        break;



    case SIFIVE_GPIO_REG_LOW_IE:

        s->low_ie = value;

        break;



    case SIFIVE_GPIO_REG_LOW_IP:

         /* Write 1 to clear */

        s->low_ip &= ~value;

        break;



    case SIFIVE_GPIO_REG_IOF_EN:

        s->iof_en = value;

        break;



    case SIFIVE_GPIO_REG_IOF_SEL:

        s->iof_sel = value;

        break;



    case SIFIVE_GPIO_REG_OUT_XOR:

        s->out_xor = value;

        break;



    default:

        qemu_log_mask(LOG_GUEST_ERROR,

                      "%s: bad write offset 0x%" HWADDR_PRIx "\n",

                      __func__, offset);

    }



    update_state(s);

}



static const MemoryRegionOps gpio_ops = {

    .read =  sifive_gpio_read,

    .write = sifive_gpio_write,

    .endianness = DEVICE_LITTLE_ENDIAN,

    .impl.min_access_size = 4,

    .impl.max_access_size = 4,

};



static void sifive_gpio_set(void *opaque, int line, int value)

{

    SIFIVEGPIOState *s = SIFIVE_GPIO(opaque);



    trace_sifive_gpio_set(line, value);



    assert(line >= 0 && line < SIFIVE_GPIO_PINS);



    s->in_mask = deposit32(s->in_mask, line, 1, value >= 0);

    if (value >= 0) {

        s->in = deposit32(s->in, line, 1, value != 0);

    }



    update_state(s);

}



static void sifive_gpio_reset(DeviceState *dev)

{

    SIFIVEGPIOState *s = SIFIVE_GPIO(dev);



    s->value = 0;

    s->input_en = 0;

    s->output_en = 0;

    s->port = 0;

    s->pue = 0;

    s->ds = 0;

    s->rise_ie = 0;

    s->rise_ip = 0;

    s->fall_ie = 0;

    s->fall_ip = 0;

    s->high_ie = 0;

    s->high_ip = 0;

    s->low_ie = 0;

    s->low_ip = 0;

    s->iof_en = 0;

    s->iof_sel = 0;

    s->out_xor = 0;

    s->in = 0;

    s->in_mask = 0;



}



static const VMStateDescription vmstate_sifive_gpio = {

    .name = TYPE_SIFIVE_GPIO,

    .version_id = 1,

    .minimum_version_id = 1,

    .fields = (VMStateField[]) {

        VMSTATE_UINT32(value,     SIFIVEGPIOState),

        VMSTATE_UINT32(input_en,  SIFIVEGPIOState),

        VMSTATE_UINT32(output_en, SIFIVEGPIOState),

        VMSTATE_UINT32(port,      SIFIVEGPIOState),

        VMSTATE_UINT32(pue,       SIFIVEGPIOState),

        VMSTATE_UINT32(rise_ie,   SIFIVEGPIOState),

        VMSTATE_UINT32(rise_ip,   SIFIVEGPIOState),

        VMSTATE_UINT32(fall_ie,   SIFIVEGPIOState),

        VMSTATE_UINT32(fall_ip,   SIFIVEGPIOState),

        VMSTATE_UINT32(high_ie,   SIFIVEGPIOState),

        VMSTATE_UINT32(high_ip,   SIFIVEGPIOState),

        VMSTATE_UINT32(low_ie,    SIFIVEGPIOState),

        VMSTATE_UINT32(low_ip,    SIFIVEGPIOState),

        VMSTATE_UINT32(iof_en,    SIFIVEGPIOState),

        VMSTATE_UINT32(iof_sel,   SIFIVEGPIOState),

        VMSTATE_UINT32(out_xor,   SIFIVEGPIOState),

        VMSTATE_UINT32(in, SIFIVEGPIOState),

        VMSTATE_UINT32(in_mask, SIFIVEGPIOState),

        VMSTATE_END_OF_LIST()

    }

};



static void sifive_gpio_init(Object *obj)

{

    SIFIVEGPIOState *s = SIFIVE_GPIO(obj);



    memory_region_init_io(&s->mmio, obj, &gpio_ops, s,

            TYPE_SIFIVE_GPIO, SIFIVE_GPIO_SIZE);

    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);





    for (int i = 0; i < SIFIVE_GPIO_PINS; i++) {

        sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq[i]);

    }



    qdev_init_gpio_in(DEVICE(s), sifive_gpio_set, SIFIVE_GPIO_PINS);

    qdev_init_gpio_out(DEVICE(s), s->output, SIFIVE_GPIO_PINS);

}



static void sifive_gpio_class_init(ObjectClass *klass, void *data)

{

    DeviceClass *dc = DEVICE_CLASS(klass);



    dc->vmsd = &vmstate_sifive_gpio;

    dc->reset = sifive_gpio_reset;

    dc->desc = "sifive GPIO";

}



static const TypeInfo sifive_gpio_info = {

    .name = TYPE_SIFIVE_GPIO,

    .parent = TYPE_SYS_BUS_DEVICE,

    .instance_size = sizeof(SIFIVEGPIOState),

    .instance_init = sifive_gpio_init,

    .class_init = sifive_gpio_class_init

};



static void sifive_gpio_register_types(void)

{

    type_register_static(&sifive_gpio_info);

}



type_init(sifive_gpio_register_types)

hw/riscv/trace-events

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# See docs/devel/tracing.txt for syntax documentation.



# hw/gpio/sifive_gpio.c

sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PRIx64

sifive_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x%" PRIx64

sifive_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64

sifive_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64