Commit 30c0c76c authored by Jay Foad's avatar Jay Foad Committed by malc
Browse files

tcg: fix build on 32-bit hppa, ppc and sparc hosts 



The qemu_ld32s op is only defined if TCG_TARGET_REG_BITS == 64.

Signed-off-by: default avatarJay Foad <jay.foad@gmail.com>
Signed-off-by: default avatarmalc <av1474@comtv.ru>
parent bc3b26f5

tcg/hppa/tcg-target.c

+0 −1
Original line number Diff line number Diff line
@@ -936,7 +936,6 @@ static const TCGTargetOpDef hppa_op_defs[] = { 
    { INDEX_op_qemu_ld16u, { "r", "L", "L" } },

    { INDEX_op_qemu_ld16s, { "r", "L", "L" } },

    { INDEX_op_qemu_ld32u, { "r", "L", "L" } },

    { INDEX_op_qemu_ld32s, { "r", "L", "L" } },

    { INDEX_op_qemu_ld64, { "r", "r", "L", "L" } },



    { INDEX_op_qemu_st8, { "L", "L", "L" } },

tcg/ppc/tcg-target.c

+0 −2
Original line number Diff line number Diff line
@@ -1693,7 +1693,6 @@ static const TCGTargetOpDef ppc_op_defs[] = { 
    { INDEX_op_qemu_ld16u, { "r", "L" } },

    { INDEX_op_qemu_ld16s, { "r", "L" } },

    { INDEX_op_qemu_ld32u, { "r", "L" } },

    { INDEX_op_qemu_ld32s, { "r", "L" } },

    { INDEX_op_qemu_ld64, { "r", "r", "L" } },



    { INDEX_op_qemu_st8, { "K", "K" } },
@@ -1706,7 +1705,6 @@ static const TCGTargetOpDef ppc_op_defs[] = { 
    { INDEX_op_qemu_ld16u, { "r", "L", "L" } },

    { INDEX_op_qemu_ld16s, { "r", "L", "L" } },

    { INDEX_op_qemu_ld32u, { "r", "L", "L" } },

    { INDEX_op_qemu_ld32s, { "r", "L", "L" } },

    { INDEX_op_qemu_ld64, { "r", "L", "L", "L" } },



    { INDEX_op_qemu_st8, { "K", "K", "K" } },

tcg/sparc/tcg-target.c

+4 −0
Original line number Diff line number Diff line
@@ -1319,9 +1319,11 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args, 
    case INDEX_op_qemu_ld32u:

        tcg_out_qemu_ld(s, args, 2);

        break;

#if TCG_TARGET_REG_BITS == 64

    case INDEX_op_qemu_ld32s:

        tcg_out_qemu_ld(s, args, 2 | 4);

        break;

#endif

    case INDEX_op_qemu_st8:

        tcg_out_qemu_st(s, args, 0);

        break;
@@ -1471,7 +1473,9 @@ static const TCGTargetOpDef sparc_op_defs[] = { 
    { INDEX_op_qemu_ld16u, { "r", "L" } },

    { INDEX_op_qemu_ld16s, { "r", "L" } },

    { INDEX_op_qemu_ld32u, { "r", "L" } },

#if TCG_TARGET_REG_BITS == 64

    { INDEX_op_qemu_ld32s, { "r", "L" } },

#endif



    { INDEX_op_qemu_st8, { "L", "L" } },

    { INDEX_op_qemu_st16, { "L", "L" } },