Commit 2f0180c5 authored by Edgar E. Iglesias's avatar Edgar E. Iglesias Committed by Peter Maydell
Browse files

target-arm: Make far_el1 an array 



No functional change.
Prepares for future additions of the EL2 and 3 versions of this reg.

Reviewed-by: default avatarGreg Bellows <greg.bellows@linaro.org>
Signed-off-by: default avatarEdgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: default avatarAlex Bennée <alex.bennee@linaro.org>
Message-id: 1402994746-8328-5-git-send-email-edgar.iglesias@gmail.com
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent f151b123

target-arm/cpu.c

+1 −1
Original line number Diff line number Diff line
@@ -447,7 +447,7 @@ static void arm1026_initfn(Object *obj) 
        ARMCPRegInfo ifar = {

            .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,

            .access = PL1_RW,

            .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el1),

            .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el[1]),

            .resetvalue = 0

        };

        define_one_arm_cp_reg(cpu, &ifar);

target-arm/cpu.h

+1 −1
Original line number Diff line number Diff line
@@ -187,7 +187,7 @@ typedef struct CPUARMState { 
        uint32_t ifsr_el2; /* Fault status registers.  */

        uint64_t esr_el[2];

        uint32_t c6_region[8]; /* MPU base/size registers.  */

        uint64_t far_el1; /* Fault address registers.  */

        uint64_t far_el[2]; /* Fault address registers.  */

        uint64_t par_el1;  /* Translation result. */

        uint32_t c9_insn; /* Cache lockdown registers.  */

        uint32_t c9_data;

target-arm/helper-a64.c

+2 −2
Original line number Diff line number Diff line
@@ -465,13 +465,13 @@ void aarch64_cpu_do_interrupt(CPUState *cs) 
    }



    env->cp15.esr_el[1] = env->exception.syndrome;

    env->cp15.far_el1 = env->exception.vaddress;

    env->cp15.far_el[1] = env->exception.vaddress;



    switch (cs->exception_index) {

    case EXCP_PREFETCH_ABORT:

    case EXCP_DATA_ABORT:

        qemu_log_mask(CPU_LOG_INT, "...with FAR 0x%" PRIx64 "\n",

                      env->cp15.far_el1);

                      env->cp15.far_el[1]);

        break;

    case EXCP_BKPT:

    case EXCP_UDEF:

target-arm/helper.c

+6 −6
Original line number Diff line number Diff line
@@ -521,7 +521,7 @@ static const ARMCPRegInfo v6_cp_reginfo[] = { 
      .access = PL0_W, .type = ARM_CP_NOP },

    { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,

      .access = PL1_RW,

      .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el1),

      .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el[1]),

      .resetvalue = 0, },

    /* Watchpoint Fault Address Register : should actually only be present

     * for 1136, 1176, 11MPCore.
@@ -1516,7 +1516,7 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = { 
    /* 64-bit FAR; this entry also gives us the AArch32 DFAR */

    { .name = "FAR_EL1", .state = ARM_CP_STATE_BOTH,

      .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,

      .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el1),

      .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]),

      .resetvalue = 0, },

    REGINFO_SENTINEL

};
@@ -3425,7 +3425,7 @@ void arm_cpu_do_interrupt(CPUState *cs) 
        /* Fall through to prefetch abort.  */

    case EXCP_PREFETCH_ABORT:

        env->cp15.ifsr_el2 = env->exception.fsr;

        env->cp15.far_el1 = deposit64(env->cp15.far_el1, 32, 32,

        env->cp15.far_el[1] = deposit64(env->cp15.far_el[1], 32, 32,

                                        env->exception.vaddress);

        qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n",

                      env->cp15.ifsr_el2, (uint32_t)env->exception.vaddress);
@@ -3436,7 +3436,7 @@ void arm_cpu_do_interrupt(CPUState *cs) 
        break;

    case EXCP_DATA_ABORT:

        env->cp15.esr_el[1] = env->exception.fsr;

        env->cp15.far_el1 = deposit64(env->cp15.far_el1, 0, 32,

        env->cp15.far_el[1] = deposit64(env->cp15.far_el[1], 0, 32,

                                        env->exception.vaddress);

        qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n",

                      (uint32_t)env->cp15.esr_el[1],