Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-january-25-2019' into staging (2dc2f10d) · Commits · SUMMER2020 / students / proj-2021291

MAINTAINERS

+0 −9

Original line number	Diff line number	Diff line
		@@ -206,7 +206,6 @@ MIPS
		M: Aurelien Jarno <aurelien@aurel32.net>
		M: Aleksandar Markovic <amarkovic@wavecomp.com>
		R: Aleksandar Rikalo <arikalo@wavecomp.com>
		R: Stefan Markovic <smarkovic@wavecomp.com>
		S: Maintained
		F: target/mips/
		F: default-configs/mips
		@@ -365,7 +364,6 @@ F: target/arm/kvm.c
		MIPS
		M: James Hogan <jhogan@kernel.org>
		R: Aleksandar Rikalo <arikalo@wavecomp.com>
		R: Stefan Markovic <smarkovic@wavecomp.com>
		S: Maintained
		F: target/mips/kvm.c

		@@ -890,7 +888,6 @@ MIPS Machines
		Jazz
		M: Hervé Poussineau <hpoussin@reactos.org>
		R: Aleksandar Rikalo <arikalo@wavecomp.com>
		R: Stefan Markovic <smarkovic@wavecomp.com>
		S: Maintained
		F: hw/mips/mips_jazz.c
		F: hw/display/jazz_led.c
		@@ -899,14 +896,12 @@ F: hw/dma/rc4030.c
		Malta
		M: Aurelien Jarno <aurelien@aurel32.net>
		R: Aleksandar Rikalo <arikalo@wavecomp.com>
		R: Stefan Markovic <smarkovic@wavecomp.com>
		S: Maintained
		F: hw/mips/mips_malta.c

		Mipssim
		M: Aleksandar Markovic <amarkovic@wavecomp.com>
		R: Aleksandar Rikalo <arikalo@wavecomp.com>
		R: Stefan Markovic <smarkovic@wavecomp.com>
		S: Odd Fixes
		F: hw/mips/mips_mipssim.c
		F: hw/net/mipsnet.c
		@@ -914,14 +909,12 @@ F: hw/net/mipsnet.c
		R4000
		M: Aurelien Jarno <aurelien@aurel32.net>
		R: Aleksandar Rikalo <arikalo@wavecomp.com>
		R: Stefan Markovic <smarkovic@wavecomp.com>
		S: Maintained
		F: hw/mips/mips_r4k.c

		Fulong 2E
		M: Aleksandar Markovic <amarkovic@wavecomp.com>
		R: Aleksandar Rikalo <arikalo@wavecomp.com>
		R: Stefan Markovic <smarkovic@wavecomp.com>
		S: Odd Fixes
		F: hw/mips/mips_fulong2e.c
		F: hw/isa/vt82c686.c
		@@ -931,7 +924,6 @@ F: include/hw/isa/vt82c686.h
		Boston
		M: Paul Burton <pburton@wavecomp.com>
		R: Aleksandar Rikalo <arikalo@wavecomp.com>
		R: Stefan Markovic <smarkovic@wavecomp.com>
		S: Maintained
		F: hw/core/loader-fit.c
		F: hw/mips/boston.c
		@@ -2203,7 +2195,6 @@ F: disas/i386.c
		MIPS target
		M: Aurelien Jarno <aurelien@aurel32.net>
		R: Aleksandar Rikalo <arikalo@wavecomp.com>
		R: Stefan Markovic <smarkovic@wavecomp.com>
		S: Maintained
		F: tcg/mips/
		F: disas/mips.c

disas/nanomips.cpp

+75 −44

Original line number	Diff line number	Diff line
		@@ -1836,7 +1836,8 @@ std::string NMD::ABS_S(uint64 instruction)


		/*
		* ABSQ_S.PH rt, rs - Find Absolute Value of Two Fractional Halfwords
		* [DSP] ABSQ_S.PH rt, rs - Find absolute value of two fractional halfwords
		* with 16-bit saturation
		*
		* 3 2 1
		* 10987654321098765432109876543210
		@@ -1857,7 +1858,8 @@ std::string NMD::ABSQ_S_PH(uint64 instruction)


		/*
		* ABSQ_S.QB rt, rs - Find Absolute Value of Four Fractional Byte Values
		* [DSP] ABSQ_S.QB rt, rs - Find absolute value of four fractional byte values
		* with 8-bit saturation
		*
		* 3 2 1
		* 10987654321098765432109876543210
		@@ -1878,7 +1880,8 @@ std::string NMD::ABSQ_S_QB(uint64 instruction)


		/*
		*
		* [DSP] ABSQ_S.W rt, rs - Find absolute value of fractional word with 32-bit
		* saturation
		*
		* 3 2 1
		* 10987654321098765432109876543210
		@@ -2233,7 +2236,7 @@ std::string NMD::ADDIUPC_48_(uint64 instruction)


		/*
		* ADDQ.PH rd, rt, rs - Add Fractional Halfword Vectors
		* [DSP] ADDQ.PH rd, rt, rs - Add fractional halfword vectors
		*
		* 3 2 1
		* 10987654321098765432109876543210
		@@ -2257,7 +2260,8 @@ std::string NMD::ADDQ_PH(uint64 instruction)


		/*
		* ADDQ_S.PH rd, rt, rs - Add Fractional Halfword Vectors
		* [DSP] ADDQ_S.PH rd, rt, rs - Add fractional halfword vectors with 16-bit
		* saturation
		*
		* 3 2 1
		* 10987654321098765432109876543210
		@@ -2281,7 +2285,7 @@ std::string NMD::ADDQ_S_PH(uint64 instruction)


		/*
		* ADDQ_S.W rd, rt, rs - Add Fractional Words
		* [DSP] ADDQ_S.W rd, rt, rs - Add fractional words with 32-bit saturation
		*
		* 3 2 1
		* 10987654321098765432109876543210
		@@ -2305,8 +2309,8 @@ std::string NMD::ADDQ_S_W(uint64 instruction)


		/*
		* ADDQH.PH rd, rt, rs - Add Fractional Halfword Vectors And Shift Right
		* to Halve Results
		* [DSP] ADDQH.PH rd, rt, rs - Add fractional halfword vectors and shift
		* right to halve results
		*
		* 3 2 1
		* 10987654321098765432109876543210
		@@ -2330,8 +2334,8 @@ std::string NMD::ADDQH_PH(uint64 instruction)


		/*
		* ADDQH_R.PH rd, rt, rs - Add Fractional Halfword Vectors And Shift Right
		* to Halve Results
		* [DSP] ADDQH_R.PH rd, rt, rs - Add fractional halfword vectors and shift
		* right to halve results with rounding
		*
		* 3 2 1
		* 10987654321098765432109876543210
		@@ -2355,7 +2359,8 @@ std::string NMD::ADDQH_R_PH(uint64 instruction)


		/*
		* ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
		* [DSP] ADDQH_R.W rd, rt, rs - Add fractional words and shift right to halve
		* results with rounding
		*
		* 3 2 1
		* 10987654321098765432109876543210
		@@ -2379,7 +2384,8 @@ std::string NMD::ADDQH_R_W(uint64 instruction)


		/*
		* ADDQH.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
		* [DSP] ADDQH.W rd, rt, rs - Add fractional words and shift right to halve
		* results
		*
		* 3 2 1
		* 10987654321098765432109876543210
		@@ -2403,7 +2409,7 @@ std::string NMD::ADDQH_W(uint64 instruction)


		/*
		* ADDSC rd, rt, rs - Add Signed Word and Set Carry Bit
		* [DSP] ADDSC rd, rt, rs - Add two signed words and set carry bit
		*
		* 3 2 1
		* 10987654321098765432109876543210
		@@ -2496,7 +2502,7 @@ std::string NMD::ADDU_4X4_(uint64 instruction)


		/*
		* ADDU.PH rd, rt, rs - Unsigned Add Integer Halfwords
		* [DSP] ADDU.PH rd, rt, rs - Add two pairs of unsigned halfwords
		*
		* 3 2 1
		* 10987654321098765432109876543210
		@@ -2544,7 +2550,8 @@ std::string NMD::ADDU_QB(uint64 instruction)


		/*
		* ADDU_S.PH rd, rt, rs - Unsigned Add Integer Halfwords
		* [DSP] ADDU_S.PH rd, rt, rs - Add two pairs of unsigned halfwords with 16-bit
		* saturation
		*
		* 3 2 1
		* 10987654321098765432109876543210
		@@ -7848,7 +7855,7 @@ std::string NMD::INS(uint64 instruction)


		/*
		*
		* [DSP] INSV - Insert bit field variable
		*
		* 3 2 1
		* 10987654321098765432109876543210
		@@ -9698,7 +9705,8 @@ std::string NMD::LWXS_32_(uint64 instruction)


		/*
		*
		* [DSP] MADD ac, rs, rt - Multiply two words and add to the specified
		* accumulator
		*
		* 3 2 1
		* 10987654321098765432109876543210
		@@ -9770,7 +9778,8 @@ std::string NMD::MADDF_S(uint64 instruction)


		/*
		*
		* [DSP] MADDU ac, rs, rt - Multiply two unsigned words and add to the
		* specified accumulator
		*
		* 3 2 1
		* 10987654321098765432109876543210
		@@ -9794,7 +9803,8 @@ std::string NMD::MADDU_DSP_(uint64 instruction)


		/*
		*
		* [DSP] MAQ_S.W.PHL ac, rs, rt - Multiply the left-most single vector
		* fractional halfword elements with accumulation
		*
		* 3 2 1
		* 10987654321098765432109876543210
		@@ -9818,7 +9828,8 @@ std::string NMD::MAQ_S_W_PHL(uint64 instruction)


		/*
		*
		* [DSP] MAQ_S.W.PHR ac, rs, rt - Multiply the right-most single vector
		* fractional halfword elements with accumulation
		*
		* 3 2 1
		* 10987654321098765432109876543210
		@@ -9842,7 +9853,8 @@ std::string NMD::MAQ_S_W_PHR(uint64 instruction)


		/*
		*
		* [DSP] MAQ_SA.W.PHL ac, rs, rt - Multiply the left-most single vector
		* fractional halfword elements with saturating accumulation
		*
		* 3 2 1
		* 10987654321098765432109876543210
		@@ -9866,7 +9878,8 @@ std::string NMD::MAQ_SA_W_PHL(uint64 instruction)


		/*
		*
		* [DSP] MAQ_SA.W.PHR ac, rs, rt - Multiply the right-most single vector
		* fractional halfword elements with saturating accumulation
		*
		* 3 2 1
		* 10987654321098765432109876543210
		@@ -11722,7 +11735,8 @@ std::string NMD::ORI(uint64 instruction)


		/*
		* ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
		* [DSP] PACKRL.PH rd, rs, rt - Pack a word using the right halfword from one
		* source register and left halfword from another source register
		*
		* 3 2 1
		* 10987654321098765432109876543210
		@@ -11764,7 +11778,8 @@ std::string NMD::PAUSE(uint64 instruction)


		/*
		* ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
		* [DSP] PICK.PH rd, rs, rt - Pick a vector of halfwords based on condition
		* code bits
		*
		* 3 2 1
		* 10987654321098765432109876543210
		@@ -11788,7 +11803,8 @@ std::string NMD::PICK_PH(uint64 instruction)


		/*
		* ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
		* [DSP] PICK.QB rd, rs, rt - Pick a vector of byte values based on condition
		* code bits
		*
		* 3 2 1
		* 10987654321098765432109876543210
		@@ -11812,7 +11828,8 @@ std::string NMD::PICK_QB(uint64 instruction)


		/*
		* ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
		* [DSP] PRECEQ.W.PHL rt, rs - Expand the precision of the left-most element
		* of a paired halfword
		*
		* 3 2 1
		* 10987654321098765432109876543210
		@@ -11834,7 +11851,8 @@ std::string NMD::PRECEQ_W_PHL(uint64 instruction)


		/*
		* ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
		* [DSP] PRECEQ.W.PHR rt, rs - Expand the precision of the right-most element
		* of a paired halfword
		*
		* 3 2 1
		* 10987654321098765432109876543210
		@@ -11856,7 +11874,8 @@ std::string NMD::PRECEQ_W_PHR(uint64 instruction)


		/*
		* ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
		* [DSP] PRECEQU.PH.QBLA rt, rs - Expand the precision of the two
		* left-alternate elements of a quad byte vector
		*
		* 3 2 1
		* 10987654321098765432109876543210
		@@ -11878,7 +11897,8 @@ std::string NMD::PRECEQU_PH_QBLA(uint64 instruction)


		/*
		* ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
		* [DSP] PRECEQU.PH.QBL rt, rs - Expand the precision of the two left-most
		* elements of a quad byte vector
		*
		* 3 2 1
		* 10987654321098765432109876543210
		@@ -11900,7 +11920,8 @@ std::string NMD::PRECEQU_PH_QBL(uint64 instruction)


		/*
		* ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
		* [DSP] PRECEQU.PH.QBRA rt, rs - Expand the precision of the two
		* right-alternate elements of a quad byte vector
		*
		* 3 2 1
		* 10987654321098765432109876543210
		@@ -11922,7 +11943,8 @@ std::string NMD::PRECEQU_PH_QBRA(uint64 instruction)


		/*
		* ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
		* [DSP] PRECEQU.PH.QBR rt, rs - Expand the precision of the two right-most
		* elements of a quad byte vector
		*
		* 3 2 1
		* 10987654321098765432109876543210
		@@ -11944,7 +11966,9 @@ std::string NMD::PRECEQU_PH_QBR(uint64 instruction)


		/*
		* ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
		* [DSP] PRECEU.PH.QBLA rt, rs - Expand the precision of the two
		* left-alternate elements of a quad byte vector to four unsigned
		* halfwords
		*
		* 3 2 1
		* 10987654321098765432109876543210
		@@ -11966,7 +11990,8 @@ std::string NMD::PRECEU_PH_QBLA(uint64 instruction)


		/*
		* ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
		* [DSP] PRECEU.PH.QBL rt, rs - Expand the precision of the two left-most
		* elements of a quad byte vector to form unsigned halfwords
		*
		* 3 2 1
		* 10987654321098765432109876543210
		@@ -11988,7 +12013,9 @@ std::string NMD::PRECEU_PH_QBL(uint64 instruction)


		/*
		* ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
		* [DSP] PRECEU.PH.QBRA rt, rs - Expand the precision of the two
		* right-alternate elements of a quad byte vector to form four
		* unsigned halfwords
		*
		* 3 2 1
		* 10987654321098765432109876543210
		@@ -12010,7 +12037,8 @@ std::string NMD::PRECEU_PH_QBRA(uint64 instruction)


		/*
		* ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
		* [DSP] PRECEU.PH.QBR rt, rs - Expand the precision of the two right-most
		* elements of a quad byte vector to form unsigned halfwords
		*
		* 3 2 1
		* 10987654321098765432109876543210
		@@ -15202,7 +15230,7 @@ std::string NMD::SUBU_32_(uint64 instruction)


		/*
		* SUBU.PH rd, rs, rt - Subtract Unsigned Integer Halfwords
		* [DSP] SUBU.PH rd, rs, rt - Subtract unsigned unsigned halfwords
		*
		* 3 2 1
		* 10987654321098765432109876543210
		@@ -15226,7 +15254,7 @@ std::string NMD::SUBU_PH(uint64 instruction)


		/*
		* SUBU.QB rd, rs, rt - Subtract Unsigned Quad Byte Vector
		* [DSP] SUBU.QB rd, rs, rt - Subtract unsigned quad byte vectors
		*
		* 3 2 1
		* 10987654321098765432109876543210
		@@ -15250,7 +15278,8 @@ std::string NMD::SUBU_QB(uint64 instruction)


		/*
		* SUBU_S.PH rd, rs, rt - Subtract Unsigned Integer Halfwords (saturating)
		* [DSP] SUBU_S.PH rd, rs, rt - Subtract unsigned unsigned halfwords with
		* 8-bit saturation
		*
		* 3 2 1
		* 10987654321098765432109876543210
		@@ -15274,7 +15303,8 @@ std::string NMD::SUBU_S_PH(uint64 instruction)


		/*
		* SUBU_S.QB rd, rs, rt - Subtract Unsigned Quad Byte Vector (saturating)
		* [DSP] SUBU_S.QB rd, rs, rt - Subtract unsigned quad byte vectors with
		* 8-bit saturation
		*
		* 3 2 1
		* 10987654321098765432109876543210
		@@ -15298,8 +15328,8 @@ std::string NMD::SUBU_S_QB(uint64 instruction)


		/*
		* SUBUH.QB rd, rs, rt - Subtract Unsigned Bytes And Right Shift to Halve
		* Results
		* [DSP] SUBUH.QB rd, rs, rt - Subtract unsigned bytes and right shift
		* to halve results
		*
		* 3 2 1
		* 10987654321098765432109876543210
		@@ -15323,8 +15353,8 @@ std::string NMD::SUBUH_QB(uint64 instruction)


		/*
		* SUBUH_R.QB rd, rs, rt - Subtract Unsigned Bytes And Right Shift to Halve
		* Results (rounding)
		* [DSP] SUBUH_R.QB rd, rs, rt - Subtract unsigned bytes and right shift
		* to halve results with rounding
		*
		* 3 2 1
		* 10987654321098765432109876543210
		@@ -16412,7 +16442,8 @@ std::string NMD::WAIT(uint64 instruction)


		/*
		* WRDSP rt, mask - Write Fields to DSPControl Register from a GPR
		* [DSP] WRDSP rt, mask - Write selected fields from a GPR to the DSPControl
		* register
		*
		* 3 2 1
		* 10987654321098765432109876543210

docs/qemu-cpu-models.texi

+161 −2

Original line number	Diff line number	Diff line
		@@ -6,6 +6,7 @@ QEMU / KVM CPU model configuration

		@menu
		* recommendations_cpu_models_x86:: Recommendations for KVM CPU model configuration on x86 hosts
		* recommendations_cpu_models_MIPS:: Supported CPU model configurations on MIPS hosts
		* cpu_model_syntax_apps:: Syntax for configuring CPU models
		@end menu

		@@ -368,6 +369,164 @@ hardware assisted virtualization, that should thus not be required for
		running virtual machines.
		@end table

		@node recommendations_cpu_models_MIPS
		@subsection Supported CPU model configurations on MIPS hosts

		QEMU supports variety of MIPS CPU models:

		@menu
		* cpu_models_MIPS32:: Supported CPU models for MIPS32 hosts
		* cpu_models_MIPS64:: Supported CPU models for MIPS64 hosts
		* cpu_models_nanoMIPS:: Supported CPU models for nanoMIPS hosts
		* preferred_cpu_models_MIPS:: Preferred CPU models for MIPS hosts
		@end menu

		@node cpu_models_MIPS32
		@subsubsection Supported CPU models for MIPS32 hosts

		The following CPU models are supported for use on MIPS32 hosts. Administrators /
		applications are recommended to use the CPU model that matches the generation
		of the host CPUs in use. In a deployment with a mixture of host CPU models
		between machines, if live migration compatibility is required, use the newest
		CPU model that is compatible across all desired hosts.

		@table @option
		@item @code{mips32r6-generic}

		MIPS32 Processor (Release 6, 2015)


		@item @code{P5600}

		MIPS32 Processor (P5600, 2014)


		@item @code{M14K}
		@item @code{M14Kc}

		MIPS32 Processor (M14K, 2009)


		@item @code{74Kf}

		MIPS32 Processor (74K, 2007)


		@item @code{34Kf}

		MIPS32 Processor (34K, 2006)


		@item @code{24Kc}
		@item @code{24KEc}
		@item @code{24Kf}

		MIPS32 Processor (24K, 2003)


		@item @code{4Kc}
		@item @code{4Km}
		@item @code{4KEcR1}
		@item @code{4KEmR1}
		@item @code{4KEc}
		@item @code{4KEm}

		MIPS32 Processor (4K, 1999)
		@end table

		@node cpu_models_MIPS64
		@subsubsection Supported CPU models for MIPS64 hosts

		The following CPU models are supported for use on MIPS64 hosts. Administrators /
		applications are recommended to use the CPU model that matches the generation
		of the host CPUs in use. In a deployment with a mixture of host CPU models
		between machines, if live migration compatibility is required, use the newest
		CPU model that is compatible across all desired hosts.

		@table @option
		@item @code{I6400}

		MIPS64 Processor (Release 6, 2014)


		@item @code{Loongson-2F}

		MIPS64 Processor (Longsoon 2, 2008)


		@item @code{Loongson-2E}

		MIPS64 Processor (Loongson 2, 2006)


		@item @code{mips64dspr2}

		MIPS64 Processor (Release 2, 2006)


		@item @code{MIPS64R2-generic}
		@item @code{5KEc}
		@item @code{5KEf}

		MIPS64 Processor (Release 2, 2002)


		@item @code{20Kc}

		MIPS64 Processor (20K, 2000)


		@item @code{5Kc}
		@item @code{5Kf}

		MIPS64 Processor (5K, 1999)


		@item @code{VR5432}

		MIPS64 Processor (VR, 1998)


		@item @code{R4000}

		MIPS64 Processor (MIPS III, 1991)
		@end table

		@node cpu_models_nanoMIPS
		@subsubsection Supported CPU models for nanoMIPS hosts

		The following CPU models are supported for use on nanoMIPS hosts. Administrators /
		applications are recommended to use the CPU model that matches the generation
		of the host CPUs in use. In a deployment with a mixture of host CPU models
		between machines, if live migration compatibility is required, use the newest
		CPU model that is compatible across all desired hosts.

		@table @option
		@item @code{I7200}

		MIPS I7200 (nanoMIPS, 2018)

		@end table

		@node preferred_cpu_models_MIPS
		@subsubsection Preferred CPU models for MIPS hosts

		The following CPU models are preferred for use on different MIPS hosts:

		@table @option
		@item @code{MIPS III}
		R4000

		@item @code{MIPS32R2}
		34Kf

		@item @code{MIPS64R6}
		I6400

		@item @code{nanoMIPS}
		I7200
		@end table

		@node cpu_model_syntax_apps
		@subsection Syntax for configuring CPU models

qemu-doc.texi

+29 −0

Original line number	Diff line number	Diff line
		@@ -1995,6 +1995,10 @@ Set the emulated machine type. The default is sun4u.
		@section MIPS System emulator
		@cindex system emulation (MIPS)

		@menu
		* nanoMIPS System emulator ::
		@end menu

		Four executables cover simulation of 32 and 64-bit MIPS systems in
		both endian options, @file{qemu-system-mips}, @file{qemu-system-mipsel}
		@file{qemu-system-mips64} and @file{qemu-system-mips64el}.
		@@ -2086,6 +2090,31 @@ SCSI controller
		G364 framebuffer
		@end itemize

		@node nanoMIPS System emulator
		@subsection nanoMIPS System emulator
		@cindex system emulation (nanoMIPS)

		Executable @file{qemu-system-mipsel} also covers simulation of
		32-bit nanoMIPS system in little endian mode:

		@itemize @minus
		@item
		nanoMIPS I7200 CPU
		@end itemize

		Example of @file{qemu-system-mipsel} usage for nanoMIPS is shown below:

		Download @code{<disk_image_file>} from @url{https://mipsdistros.mips.com/LinuxDistro/nanomips/buildroot/index.html}.

		Download @code{<kernel_image_file>} from @url{https://mipsdistros.mips.com/LinuxDistro/nanomips/kernels/v4.15.18-432-gb2eb9a8b07a1-20180627102142/index.html}.

		Start system emulation of Malta board with nanoMIPS I7200 CPU:
		@example
		qemu-system-mipsel -cpu I7200 -kernel @code{<kernel_image_file>} \
		-M malta -serial stdio -m @code{<memory_size>} -hda @code{<disk_image_file>} \
		-append "mem=256m@@0x0 rw console=ttyS0 vga=cirrus vesa=0x111 root=/dev/sda"
		@end example


		@node ARM System emulator
		@section ARM System emulator

target/mips/cpu.h

+1 −1

Original line number	Diff line number	Diff line
		@@ -1173,7 +1173,7 @@ int cpu_mips_signal_handler(int host_signum, void pinfo, void puc);
		#define CPU_RESOLVING_TYPE TYPE_MIPS_CPU

		bool cpu_supports_cps_smp(const char *cpu_type);
		bool cpu_supports_isa(const char *cpu_type, unsigned int isa);
		bool cpu_supports_isa(const char *cpu_type, uint64_t isa);
		void cpu_set_exception_base(int vp_index, target_ulong address);

		/* mips_int.c */