Commit 2d5ee9e7 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/lalrae/tags/mips-20150716' into staging 



MIPS patches 2015-07-16

Changes:
* bug fixes

# gpg: Signature made Thu Jul 16 09:04:56 2015 BST using RSA key ID 0B29DA6B
# gpg: Good signature from "Leon Alrae <leon.alrae@imgtec.com>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 8DD3 2F98 5495 9D66 35D4  4FC0 5211 8E3C 0B29 DA6B

* remotes/lalrae/tags/mips-20150716:
  target-mips: fix page fault address for LWL/LWR/LDL/LDR
  linux-user: Fix MIPS N64 trap and break instruction bug
  target-mips: fix resource leak reported by Coverity
  target-mips: fix logically dead code reported by Coverity
  target-mips: correct DERET instruction
  target-mips: fix ASID synchronisation for MIPS MT
  disas/mips: fix disassembling R6 instructions
  target-mips: fix to clear MSACSR.Cause
  target-mips: fix MIPS64R6-generic configuration

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 3749c11a 908680c6

disas/mips.c

+6 −6
Original line number Diff line number Diff line
@@ -1296,12 +1296,12 @@ const struct mips_opcode mips_builtin_opcodes[] = 
{"dmod",    "d,s,t",    0x000000de, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I64R6},

{"ddivu",   "d,s,t",    0x0000009f, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I64R6},

{"dmodu",   "d,s,t",    0x000000df, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I64R6},

{"ll",      "t,o(b)",   0x7c000036, 0xfc00007f, LDD|RD_b|WR_t,        0, I32R6},

{"sc",      "t,o(b)",   0x7c000026, 0xfc00007f, LDD|RD_b|WR_t,        0, I32R6},

{"lld",     "t,o(b)",   0x7c000037, 0xfc00007f, LDD|RD_b|WR_t,        0, I64R6},

{"scd",     "t,o(b)",   0x7c000027, 0xfc00007f, LDD|RD_b|WR_t,        0, I64R6},

{"pref",    "h,o(b)",   0x7c000035, 0xfc00007f, RD_b,                 0, I32R6},

{"cache",   "k,o(b)",   0x7c000025, 0xfc00007f, RD_b,                 0, I32R6},

{"ll",      "t,+o(b)",  0x7c000036, 0xfc00007f, LDD|RD_b|WR_t,        0, I32R6},

{"sc",      "t,+o(b)",  0x7c000026, 0xfc00007f, LDD|RD_b|WR_t,        0, I32R6},

{"lld",     "t,+o(b)",  0x7c000037, 0xfc00007f, LDD|RD_b|WR_t,        0, I64R6},

{"scd",     "t,+o(b)",  0x7c000027, 0xfc00007f, LDD|RD_b|WR_t,        0, I64R6},

{"pref",    "h,+o(b)",  0x7c000035, 0xfc00007f, RD_b,                 0, I32R6},

{"cache",   "k,+o(b)",  0x7c000025, 0xfc00007f, RD_b,                 0, I32R6},

{"seleqz",  "d,v,t",    0x00000035, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I32R6},

{"selnez",  "d,v,t",    0x00000037, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I32R6},

{"maddf.s", "D,S,T",    0x46000018, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,  0, I32R6},

linux-user/main.c

+2 −2
Original line number Diff line number Diff line
@@ -2577,7 +2577,7 @@ done_syscall: 
                        code = (trap_instr >> 6) & 0x3f;

                    }

                } else {

                    ret = get_user_ual(trap_instr, env->active_tc.PC);

                    ret = get_user_u32(trap_instr, env->active_tc.PC);

                    if (ret != 0) {

                        goto error;

                    }
@@ -2611,7 +2611,7 @@ done_syscall: 


                    trap_instr = (instr[0] << 16) | instr[1];

                } else {

                    ret = get_user_ual(trap_instr, env->active_tc.PC);

                    ret = get_user_u32(trap_instr, env->active_tc.PC);

                }



                if (ret != 0) {

target-mips/mips-defs.h

+1 −1
Original line number Diff line number Diff line
@@ -11,7 +11,7 @@ 
#if defined(TARGET_MIPS64)

#define TARGET_LONG_BITS 64

#define TARGET_PHYS_ADDR_SPACE_BITS 48

#define TARGET_VIRT_ADDR_SPACE_BITS 42

#define TARGET_VIRT_ADDR_SPACE_BITS 48

#else

#define TARGET_LONG_BITS 32

#define TARGET_PHYS_ADDR_SPACE_BITS 40

target-mips/mips-semi.c

+19 −4
Original line number Diff line number Diff line
@@ -220,6 +220,23 @@ static int copy_argn_to_target(CPUMIPSState *env, int arg_num, 
        }                                       \

    } while (0)



#define GET_TARGET_STRINGS_2(p, addr, p2, addr2)        \

    do {                                                \

        p = lock_user_string(addr);                     \

        if (!p) {                                       \

            gpr[2] = -1;                                \

            gpr[3] = EFAULT;                            \

            goto uhi_done;                              \

        }                                               \

        p2 = lock_user_string(addr2);                   \

        if (!p2) {                                      \

            unlock_user(p, addr, 0);                    \

            gpr[2] = -1;                                \

            gpr[3] = EFAULT;                            \

            goto uhi_done;                              \

        }                                               \

    } while (0)



#define FREE_TARGET_STRING(p, gpr)              \

    do {                                        \

        unlock_user(p, gpr, 0);                 \
@@ -322,8 +339,7 @@ void helper_do_semihosting(CPUMIPSState *env) 
        FREE_TARGET_STRING(p, gpr[4]);

        break;

    case UHI_assert:

        GET_TARGET_STRING(p, gpr[4]);

        GET_TARGET_STRING(p2, gpr[5]);

        GET_TARGET_STRINGS_2(p, gpr[4], p2, gpr[5]);

        printf("assertion '");

        printf("\"%s\"", p);

        printf("': file \"%s\", line %d\n", p2, (int)gpr[6]);
@@ -341,8 +357,7 @@ void helper_do_semihosting(CPUMIPSState *env) 
        break;

#ifndef _WIN32

    case UHI_link:

        GET_TARGET_STRING(p, gpr[4]);

        GET_TARGET_STRING(p2, gpr[5]);

        GET_TARGET_STRINGS_2(p, gpr[4], p2, gpr[5]);

        gpr[2] = link(p, p2);

        gpr[3] = errno_mips(errno);

        FREE_TARGET_STRING(p2, gpr[5]);

target-mips/msa_helper.c

+6 −0
Original line number Diff line number Diff line
@@ -2642,6 +2642,8 @@ void helper_msa_fexdo_df(CPUMIPSState *env, uint32_t df, uint32_t wd, 
    wr_t *pwt = &(env->active_fpu.fpr[wt].wr);

    uint32_t i;



    clear_msacsr_cause(env);



    switch (df) {

    case DF_WORD:

        for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
@@ -3192,6 +3194,8 @@ void helper_msa_fexupl_df(CPUMIPSState *env, uint32_t df, uint32_t wd, 
    wr_t *pws = &(env->active_fpu.fpr[ws].wr);

    uint32_t i;



    clear_msacsr_cause(env);



    switch (df) {

    case DF_WORD:

        for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
@@ -3224,6 +3228,8 @@ void helper_msa_fexupr_df(CPUMIPSState *env, uint32_t df, uint32_t wd, 
    wr_t *pws = &(env->active_fpu.fpr[ws].wr);

    uint32_t i;



    clear_msacsr_cause(env);



    switch (df) {

    case DF_WORD:

        for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {