Commit 2d1fe187 authored by Anthony Liguori's avatar Anthony Liguori
Browse files

Merge remote-tracking branch 'pmaydell/tags/pull-target-arm-20130910' into staging 



ARM queue:
 * aarch64 preparation patchset (excluding the defconfigs, so this
   doesn't actually enable the new targets yet)
 * minor bugfixes and cleanups
 * disable "-cpu any" in system emulation mode
 * fix ARMv7M stack alignment on reset

# gpg: Signature made Tue 10 Sep 2013 01:46:11 PM CDT using RSA key ID 14360CDE
# gpg: Can't check signature: public key not found

# By Alexander Graf (13) and others
# Via Peter Maydell
* pmaydell/tags/pull-target-arm-20130910: (28 commits)
  configure: Add handling code for AArch64 targets
  linux-user: Add AArch64 support
  linux-user: Allow targets to specify a minimum uname release
  linux-user: Add AArch64 termbits.h definitions
  linux-user: Implement cpu_set_tls() and cpu_clone_regs() for AArch64
  linux-user: Make sure NWFPE code is 32 bit ARM only
  linux-user: Add signal handling for AArch64
  linux-user: Fix up AArch64 syscall handlers
  linux-user: Add syscall number definitions for AArch64
  linux-user: Add cpu loop for AArch64
  linux-user: Don't treat AArch64 cpu names specially
  target-arm: Add AArch64 gdbstub support
  target-arm: Add AArch64 translation stub
  target-arm: Prepare translation for AArch64 code
  target-arm: Disable 32 bit CPUs in 64 bit linux-user builds
  target-arm: Add new AArch64CPUInfo base class and subclasses
  target-arm: Pass DisasContext* to gen_set_pc_im()
  target-arm: Fix target_ulong/uint32_t confusions
  target-arm: Export cpu_env
  target-arm: Extract the disas struct to a header file
  ...

Message-id: 1378839142-7726-1-git-send-email-peter.maydell@linaro.org
Signed-off-by: default avatarAnthony Liguori <anthony@codemonkey.ws>
parents 6f52e51b 6a49fa95

configure

+6 −1
Original line number Diff line number Diff line
@@ -2550,7 +2550,7 @@ fi 
fdt_required=no

for target in $target_list; do

  case $target in

    arm*-softmmu|ppc*-softmmu|microblaze*-softmmu)

    aarch64*-softmmu|arm*-softmmu|ppc*-softmmu|microblaze*-softmmu)

      fdt_required=yes

    ;;

  esac
@@ -4366,6 +4366,11 @@ case "$target_name" in 
    bflt="yes"

    gdb_xml_files="arm-core.xml arm-vfp.xml arm-vfp3.xml arm-neon.xml"

  ;;

  aarch64)

    TARGET_BASE_ARCH=arm

    bflt="yes"

    gdb_xml_files="aarch64-core.xml"

  ;;

  cris)

  ;;

  lm32)

gdb-xml/aarch64-core.xml

0 → 100644
+46 −0
Original line number Diff line number Diff line 
<?xml version="1.0"?>

<!-- Copyright (C) 2009-2012 Free Software Foundation, Inc.

     Contributed by ARM Ltd.



     Copying and distribution of this file, with or without modification,

     are permitted in any medium without royalty provided the copyright

     notice and this notice are preserved.  -->



<!DOCTYPE feature SYSTEM "gdb-target.dtd">

<feature name="org.gnu.gdb.aarch64.core">

  <reg name="x0" bitsize="64"/>

  <reg name="x1" bitsize="64"/>

  <reg name="x2" bitsize="64"/>

  <reg name="x3" bitsize="64"/>

  <reg name="x4" bitsize="64"/>

  <reg name="x5" bitsize="64"/>

  <reg name="x6" bitsize="64"/>

  <reg name="x7" bitsize="64"/>

  <reg name="x8" bitsize="64"/>

  <reg name="x9" bitsize="64"/>

  <reg name="x10" bitsize="64"/>

  <reg name="x11" bitsize="64"/>

  <reg name="x12" bitsize="64"/>

  <reg name="x13" bitsize="64"/>

  <reg name="x14" bitsize="64"/>

  <reg name="x15" bitsize="64"/>

  <reg name="x16" bitsize="64"/>

  <reg name="x17" bitsize="64"/>

  <reg name="x18" bitsize="64"/>

  <reg name="x19" bitsize="64"/>

  <reg name="x20" bitsize="64"/>

  <reg name="x21" bitsize="64"/>

  <reg name="x22" bitsize="64"/>

  <reg name="x23" bitsize="64"/>

  <reg name="x24" bitsize="64"/>

  <reg name="x25" bitsize="64"/>

  <reg name="x26" bitsize="64"/>

  <reg name="x27" bitsize="64"/>

  <reg name="x28" bitsize="64"/>

  <reg name="x29" bitsize="64"/>

  <reg name="x30" bitsize="64"/>

  <reg name="sp" bitsize="64" type="data_ptr"/>



  <reg name="pc" bitsize="64" type="code_ptr"/>

  <reg name="cpsr" bitsize="32"/>

</feature>

hw/display/pl110.c

+8 −10
Original line number Diff line number Diff line
@@ -94,23 +94,21 @@ static const VMStateDescription vmstate_pl110 = { 
static const unsigned char pl110_id[] =

{ 0x10, 0x11, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };



/* The Arm documentation (DDI0224C) says the CLDC on the Versatile board

   has a different ID.  However Linux only looks for the normal ID.  */

#if 0

static const unsigned char pl110_versatile_id[] =

{ 0x93, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };

#else

#define pl110_versatile_id pl110_id

#endif



static const unsigned char pl111_id[] = {

    0x11, 0x11, 0x24, 0x00, 0x0d, 0xf0, 0x05, 0xb1

};





/* Indexed by pl110_version */

static const unsigned char *idregs[] = {

    pl110_id,

    pl110_versatile_id,

    /* The ARM documentation (DDI0224C) says the CLCDC on the Versatile board

     * has a different ID (0x93, 0x10, 0x04, 0x00, ...). However the hardware

     * itself has the same ID values as a stock PL110, and guests (in

     * particular Linux) rely on this. We emulate what the hardware does,

     * rather than what the docs claim it ought to do.

     */

    pl110_id,

    pl111_id

};

include/exec/user/abitypes.h

+0 −4
Original line number Diff line number Diff line
@@ -14,10 +14,6 @@ 
#define ABI_LLONG_ALIGNMENT 2

#endif



#ifdef TARGET_ARM

#define ABI_LLONG_ALIGNMENT 4

#endif



#ifndef ABI_SHORT_ALIGNMENT

#define ABI_SHORT_ALIGNMENT 2

#endif

linux-user/aarch64/syscall.h

0 → 100644
+9 −0
Original line number Diff line number Diff line 
struct target_pt_regs {

    uint64_t        regs[31];

    uint64_t        sp;

    uint64_t        pc;

    uint64_t        pstate;

};



#define UNAME_MACHINE "aarch64"

#define UNAME_MINIMUM_RELEASE "3.8.0"