Commit 2d1847ec authored by Leon Alrae's avatar Leon Alrae Committed by Yongbok Kim
Browse files

target-mips: apply CP0.PageMask before writing into TLB entry 



PFN0 and PFN1 have to be masked out with PageMask_Mask.

Signed-off-by: default avatarLeon Alrae <leon.alrae@imgtec.com>
Reviewed-by: default avatarYongbok Kim <yongbok.kim@imgtec.com>
[Yongbok Kim:
  Added commit message]
Signed-off-by: default avatarYongbok Kim <yongbok.kim@imgtec.com>
parent d3d93c6c

target/mips/op_helper.c

+3 −2
Original line number Diff line number Diff line
@@ -2008,6 +2008,7 @@ static inline uint64_t get_tlb_pfn_from_entrylo(uint64_t entrylo) 
static void r4k_fill_tlb(CPUMIPSState *env, int idx)

{

    r4k_tlb_t *tlb;

    uint64_t mask = env->CP0_PageMask >> (TARGET_PAGE_BITS + 1);



    /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */

    tlb = &env->tlb->mmu.r4k.tlb[idx];
@@ -2028,13 +2029,13 @@ static void r4k_fill_tlb(CPUMIPSState *env, int idx) 
    tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;

    tlb->XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) & 1;

    tlb->RI0 = (env->CP0_EntryLo0 >> CP0EnLo_RI) & 1;

    tlb->PFN[0] = get_tlb_pfn_from_entrylo(env->CP0_EntryLo0) << 12;

    tlb->PFN[0] = (get_tlb_pfn_from_entrylo(env->CP0_EntryLo0) & ~mask) << 12;

    tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;

    tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;

    tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;

    tlb->XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) & 1;

    tlb->RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) & 1;

    tlb->PFN[1] = get_tlb_pfn_from_entrylo(env->CP0_EntryLo1) << 12;

    tlb->PFN[1] = (get_tlb_pfn_from_entrylo(env->CP0_EntryLo1) & ~mask) << 12;

}



void r4k_helper_tlbinv(CPUMIPSState *env)