Commit 2bea128c authored by Eddie James's avatar Eddie James Committed by Peter Maydell
Browse files

hw/sd/aspeed_sdhci: New device 



The Aspeed SOCs have two SD/MMC controllers. Add a device that
encapsulates both of these controllers and models the Aspeed-specific
registers and behavior.

Tested by reading from mmcblk0 in Linux:
qemu-system-arm -machine romulus-bmc -nographic \
 -drive file=flash-romulus,format=raw,if=mtd \
 -device sd-card,drive=sd0 -drive file=_tmp/kernel,format=raw,if=sd,id=sd0

Signed-off-by: default avatarEddie James <eajames@linux.ibm.com>
Reviewed-by: default avatarCédric Le Goater <clg@kaod.org>
Reviewed-by: default avatarJoel Stanley <joel@jms.id.au>
Signed-off-by: default avatarCédric Le Goater <clg@kaod.org>
Message-id: 20190925143248.10000-3-clg@kaod.org
[clg: - changed the controller MMIO window size to 0x1000
      - moved the MMIO mapping of the SDHCI slots at the SoC level
      - merged code to add SD drives on the SD buses at the machine level ]
Signed-off-by: default avatarCédric Le Goater <clg@kaod.org>
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent 1ff68783

hw/arm/aspeed.c

+14 −1
Original line number Diff line number Diff line
@@ -170,6 +170,7 @@ static void aspeed_board_init(MachineState *machine, 
    AspeedSoCClass *sc;

    DriveInfo *drive0 = drive_get(IF_MTD, 0, 0);

    ram_addr_t max_ram_size;

    int i;



    bmc = g_new0(AspeedBoardState, 1);
@@ -252,6 +253,19 @@ static void aspeed_board_init(MachineState *machine, 
        cfg->i2c_init(bmc);

    }



    for (i = 0; i < ARRAY_SIZE(bmc->soc.sdhci.slots); i++) {

        SDHCIState *sdhci = &bmc->soc.sdhci.slots[i];

        DriveInfo *dinfo = drive_get_next(IF_SD);

        BlockBackend *blk;

        DeviceState *card;



        blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL;

        card = qdev_create(qdev_get_child_bus(DEVICE(sdhci), "sd-bus"),

                           TYPE_SD_CARD);

        qdev_prop_set_drive(card, "drive", blk, &error_fatal);

        object_property_set_bool(OBJECT(card), true, "realized", &error_fatal);

    }



    arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo);

}
@@ -373,7 +387,6 @@ static void aspeed_machine_class_init(ObjectClass *oc, void *data) 
    mc->desc = board->desc;

    mc->init = aspeed_machine_init;

    mc->max_cpus = ASPEED_CPUS_NUM;

    mc->no_sdcard = 1;

    mc->no_floppy = 1;

    mc->no_cdrom = 1;

    mc->no_parallel = 1;

hw/arm/aspeed_soc.c

+23 −0
Original line number Diff line number Diff line
@@ -36,6 +36,7 @@ static const hwaddr aspeed_soc_ast2400_memmap[] = { 
    [ASPEED_XDMA]   = 0x1E6E7000,

    [ASPEED_ADC]    = 0x1E6E9000,

    [ASPEED_SRAM]   = 0x1E720000,

    [ASPEED_SDHCI]  = 0x1E740000,

    [ASPEED_GPIO]   = 0x1E780000,

    [ASPEED_RTC]    = 0x1E781000,

    [ASPEED_TIMER1] = 0x1E782000,
@@ -63,6 +64,7 @@ static const hwaddr aspeed_soc_ast2500_memmap[] = { 
    [ASPEED_XDMA]   = 0x1E6E7000,

    [ASPEED_ADC]    = 0x1E6E9000,

    [ASPEED_SRAM]   = 0x1E720000,

    [ASPEED_SDHCI]  = 0x1E740000,

    [ASPEED_GPIO]   = 0x1E780000,

    [ASPEED_RTC]    = 0x1E781000,

    [ASPEED_TIMER1] = 0x1E782000,
@@ -108,6 +110,7 @@ static const int aspeed_soc_ast2400_irqmap[] = { 
    [ASPEED_ETH1]   = 2,

    [ASPEED_ETH2]   = 3,

    [ASPEED_XDMA]   = 6,

    [ASPEED_SDHCI]  = 26,

};



#define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap
@@ -230,6 +233,15 @@ static void aspeed_soc_init(Object *obj) 
    snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);

    sysbus_init_child_obj(obj, "gpio", OBJECT(&s->gpio), sizeof(s->gpio),

                          typename);



    sysbus_init_child_obj(obj, "sdc", OBJECT(&s->sdhci), sizeof(s->sdhci),

                          TYPE_ASPEED_SDHCI);



    /* Init sd card slot class here so that they're under the correct parent */

    for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) {

        sysbus_init_child_obj(obj, "sdhci[*]", OBJECT(&s->sdhci.slots[i]),

                              sizeof(s->sdhci.slots[i]), TYPE_SYSBUS_SDHCI);

    }

}



static void aspeed_soc_realize(DeviceState *dev, Error **errp)
@@ -419,6 +431,17 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) 
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->info->memmap[ASPEED_GPIO]);

    sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,

                       aspeed_soc_get_irq(s, ASPEED_GPIO));



    /* SDHCI */

    object_property_set_bool(OBJECT(&s->sdhci), true, "realized", &err);

    if (err) {

        error_propagate(errp, err);

        return;

    }

    sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0,

                    sc->info->memmap[ASPEED_SDHCI]);

    sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,

                       aspeed_soc_get_irq(s, ASPEED_SDHCI));

}

static Property aspeed_soc_properties[] = {

    DEFINE_PROP_UINT32("num-cpus", AspeedSoCState, num_cpus, 0),

hw/sd/Makefile.objs

+1 −0
Original line number Diff line number Diff line
@@ -8,3 +8,4 @@ obj-$(CONFIG_MILKYMIST) += milkymist-memcard.o 
obj-$(CONFIG_OMAP) += omap_mmc.o

obj-$(CONFIG_PXA2XX) += pxa2xx_mmci.o

obj-$(CONFIG_RASPI) += bcm2835_sdhost.o

obj-$(CONFIG_ASPEED_SOC) += aspeed_sdhci.o

hw/sd/aspeed_sdhci.c

0 → 100644
+198 −0
Original line number Diff line number Diff line 
/*

 * Aspeed SD Host Controller

 * Eddie James <eajames@linux.ibm.com>

 *

 * Copyright (C) 2019 IBM Corp

 * SPDX-License-Identifer: GPL-2.0-or-later

 */



#include "qemu/osdep.h"

#include "qemu/log.h"

#include "qemu/error-report.h"

#include "hw/sd/aspeed_sdhci.h"

#include "qapi/error.h"

#include "hw/irq.h"

#include "migration/vmstate.h"



#define ASPEED_SDHCI_INFO            0x00

#define  ASPEED_SDHCI_INFO_RESET     0x00030000

#define ASPEED_SDHCI_DEBOUNCE        0x04

#define  ASPEED_SDHCI_DEBOUNCE_RESET 0x00000005

#define ASPEED_SDHCI_BUS             0x08

#define ASPEED_SDHCI_SDIO_140        0x10

#define ASPEED_SDHCI_SDIO_148        0x18

#define ASPEED_SDHCI_SDIO_240        0x20

#define ASPEED_SDHCI_SDIO_248        0x28

#define ASPEED_SDHCI_WP_POL          0xec

#define ASPEED_SDHCI_CARD_DET        0xf0

#define ASPEED_SDHCI_IRQ_STAT        0xfc



#define TO_REG(addr) ((addr) / sizeof(uint32_t))



static uint64_t aspeed_sdhci_read(void *opaque, hwaddr addr, unsigned int size)

{

    uint32_t val = 0;

    AspeedSDHCIState *sdhci = opaque;



    switch (addr) {

    case ASPEED_SDHCI_SDIO_140:

        val = (uint32_t)sdhci->slots[0].capareg;

        break;

    case ASPEED_SDHCI_SDIO_148:

        val = (uint32_t)sdhci->slots[0].maxcurr;

        break;

    case ASPEED_SDHCI_SDIO_240:

        val = (uint32_t)sdhci->slots[1].capareg;

        break;

    case ASPEED_SDHCI_SDIO_248:

        val = (uint32_t)sdhci->slots[1].maxcurr;

        break;

    default:

        if (addr < ASPEED_SDHCI_REG_SIZE) {

            val = sdhci->regs[TO_REG(addr)];

        } else {

            qemu_log_mask(LOG_GUEST_ERROR,

                          "%s: Out-of-bounds read at 0x%" HWADDR_PRIx "\n",

                          __func__, addr);

        }

    }



    return (uint64_t)val;

}



static void aspeed_sdhci_write(void *opaque, hwaddr addr, uint64_t val,

                               unsigned int size)

{

    AspeedSDHCIState *sdhci = opaque;



    switch (addr) {

    case ASPEED_SDHCI_SDIO_140:

        sdhci->slots[0].capareg = (uint64_t)(uint32_t)val;

        break;

    case ASPEED_SDHCI_SDIO_148:

        sdhci->slots[0].maxcurr = (uint64_t)(uint32_t)val;

        break;

    case ASPEED_SDHCI_SDIO_240:

        sdhci->slots[1].capareg = (uint64_t)(uint32_t)val;

        break;

    case ASPEED_SDHCI_SDIO_248:

        sdhci->slots[1].maxcurr = (uint64_t)(uint32_t)val;

        break;

    default:

        if (addr < ASPEED_SDHCI_REG_SIZE) {

            sdhci->regs[TO_REG(addr)] = (uint32_t)val;

        } else {

            qemu_log_mask(LOG_GUEST_ERROR,

                          "%s: Out-of-bounds write at 0x%" HWADDR_PRIx "\n",

                          __func__, addr);

        }

    }

}



static const MemoryRegionOps aspeed_sdhci_ops = {

    .read = aspeed_sdhci_read,

    .write = aspeed_sdhci_write,

    .endianness = DEVICE_NATIVE_ENDIAN,

    .valid.min_access_size = 4,

    .valid.max_access_size = 4,

};



static void aspeed_sdhci_set_irq(void *opaque, int n, int level)

{

    AspeedSDHCIState *sdhci = opaque;



    if (level) {

        sdhci->regs[TO_REG(ASPEED_SDHCI_IRQ_STAT)] |= BIT(n);



        qemu_irq_raise(sdhci->irq);

    } else {

        sdhci->regs[TO_REG(ASPEED_SDHCI_IRQ_STAT)] &= ~BIT(n);



        qemu_irq_lower(sdhci->irq);

    }

}



static void aspeed_sdhci_realize(DeviceState *dev, Error **errp)

{

    Error *err = NULL;

    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);

    AspeedSDHCIState *sdhci = ASPEED_SDHCI(dev);



    /* Create input irqs for the slots */

    qdev_init_gpio_in_named_with_opaque(DEVICE(sbd), aspeed_sdhci_set_irq,

                                        sdhci, NULL, ASPEED_SDHCI_NUM_SLOTS);



    sysbus_init_irq(sbd, &sdhci->irq);

    memory_region_init_io(&sdhci->iomem, OBJECT(sdhci), &aspeed_sdhci_ops,

                          sdhci, TYPE_ASPEED_SDHCI, 0x1000);

    sysbus_init_mmio(sbd, &sdhci->iomem);



    for (int i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) {

        Object *sdhci_slot = OBJECT(&sdhci->slots[i]);

        SysBusDevice *sbd_slot = SYS_BUS_DEVICE(&sdhci->slots[i]);



        object_property_set_int(sdhci_slot, 2, "sd-spec-version", &err);

        if (err) {

            error_propagate(errp, err);

            return;

        }



        object_property_set_uint(sdhci_slot, ASPEED_SDHCI_CAPABILITIES,

                                 "capareg", &err);

        if (err) {

            error_propagate(errp, err);

            return;

        }



        object_property_set_bool(sdhci_slot, true, "realized", &err);

        if (err) {

            error_propagate(errp, err);

            return;

        }



        sysbus_connect_irq(sbd_slot, 0, qdev_get_gpio_in(DEVICE(sbd), i));

        memory_region_add_subregion(&sdhci->iomem, (i + 1) * 0x100,

                                    &sdhci->slots[i].iomem);

    }

}



static void aspeed_sdhci_reset(DeviceState *dev)

{

    AspeedSDHCIState *sdhci = ASPEED_SDHCI(dev);



    memset(sdhci->regs, 0, ASPEED_SDHCI_REG_SIZE);

    sdhci->regs[TO_REG(ASPEED_SDHCI_INFO)] = ASPEED_SDHCI_INFO_RESET;

    sdhci->regs[TO_REG(ASPEED_SDHCI_DEBOUNCE)] = ASPEED_SDHCI_DEBOUNCE_RESET;

}



static const VMStateDescription vmstate_aspeed_sdhci = {

    .name = TYPE_ASPEED_SDHCI,

    .version_id = 1,

    .fields = (VMStateField[]) {

        VMSTATE_UINT32_ARRAY(regs, AspeedSDHCIState, ASPEED_SDHCI_NUM_REGS),

        VMSTATE_END_OF_LIST(),

    },

};



static void aspeed_sdhci_class_init(ObjectClass *classp, void *data)

{

    DeviceClass *dc = DEVICE_CLASS(classp);



    dc->realize = aspeed_sdhci_realize;

    dc->reset = aspeed_sdhci_reset;

    dc->vmsd = &vmstate_aspeed_sdhci;

}



static TypeInfo aspeed_sdhci_info = {

    .name          = TYPE_ASPEED_SDHCI,

    .parent        = TYPE_SYS_BUS_DEVICE,

    .instance_size = sizeof(AspeedSDHCIState),

    .class_init    = aspeed_sdhci_class_init,

};



static void aspeed_sdhci_register_types(void)

{

    type_register_static(&aspeed_sdhci_info);

}



type_init(aspeed_sdhci_register_types)

include/hw/arm/aspeed_soc.h

+3 −0
Original line number Diff line number Diff line
@@ -24,6 +24,7 @@ 
#include "hw/net/ftgmac100.h"

#include "target/arm/cpu.h"

#include "hw/gpio/aspeed_gpio.h"

#include "hw/sd/aspeed_sdhci.h"



#define ASPEED_SPIS_NUM  2

#define ASPEED_WDTS_NUM  3
@@ -50,6 +51,7 @@ typedef struct AspeedSoCState { 
    AspeedWDTState wdt[ASPEED_WDTS_NUM];

    FTGMAC100State ftgmac100[ASPEED_MACS_NUM];

    AspeedGPIOState gpio;

    AspeedSDHCIState sdhci;

} AspeedSoCState;



#define TYPE_ASPEED_SOC "aspeed-soc"
@@ -93,6 +95,7 @@ enum { 
    ASPEED_SCU,

    ASPEED_ADC,

    ASPEED_SRAM,

    ASPEED_SDHCI,

    ASPEED_GPIO,

    ASPEED_RTC,

    ASPEED_TIMER1,