Commit 2b483739 authored by Peter Maydell's avatar Peter Maydell
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Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20170904-2' into staging 



target-arm:
 * collection of M profile cleanups and minor bugfixes
 * loader: handle ELF files with overlapping zero-init data
 * virt: allow PMU instantiation with userspace irqchip
 * wdt_aspeed: Add support for the reset width register
 * cpu: Define new cpu_transaction_failed() hook
 * Mark some SoC devices as not user-creatable
 * arm: Fix aa64 ldp register writeback
 * arm_gicv3_kvm: Fix compile warning

# gpg: Signature made Mon 04 Sep 2017 17:20:40 BST
# gpg:                using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>"
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20170904-2: (33 commits)
  arm_gicv3_kvm: Fix compile warning
  target/arm: Fix aa64 ldp register writeback
  hw/arm/digic: Mark device with user_creatable = false
  hw/arm/aspeed_soc: Mark devices as user_creatable = false
  target/arm: Allow deliver_fault() caller to specify EA bit
  target/arm: Factor out fault delivery code
  cputlb: Support generating CPU exceptions on memory transaction failures
  cpu: Define new cpu_transaction_failed() hook
  memory.h: Move MemTxResult type to memattrs.h
  aspeed_soc: Propagate silicon-rev to watchdog
  watchdog: wdt_aspeed: Add support for the reset width register
  target/arm/kvm: pmu: improve error handling
  hw/arm/virt: allow pmu instantiation with userspace irqchip
  target/arm/kvm: pmu: split init and set-irq stages
  hw/arm/virt: add pmu interrupt state
  hw/arm: use defined type name instead of hard-coded string
  loader: Ignore zero-sized ELF segments
  loader: Handle ELF files with overlapping zero-initialized data
  nvic: Implement "user accesses BusFault" SCS region behaviour
  armv7m_nvic.h: Move from include/hw/arm to include/hw/intc
  ...

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 98bfaac7 7229ec58

accel/tcg/cputlb.c

+30 −2
Original line number Diff line number Diff line
@@ -747,6 +747,7 @@ static inline ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr) 
}



static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry,

                         int mmu_idx,

                         target_ulong addr, uintptr_t retaddr, int size)

{

    CPUState *cpu = ENV_GET_CPU(env);
@@ -754,6 +755,7 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, 
    MemoryRegion *mr = iotlb_to_region(cpu, physaddr, iotlbentry->attrs);

    uint64_t val;

    bool locked = false;

    MemTxResult r;



    physaddr = (physaddr & TARGET_PAGE_MASK) + addr;

    cpu->mem_io_pc = retaddr;
@@ -767,7 +769,12 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, 
        qemu_mutex_lock_iothread();

        locked = true;

    }

    memory_region_dispatch_read(mr, physaddr, &val, size, iotlbentry->attrs);

    r = memory_region_dispatch_read(mr, physaddr,

                                    &val, size, iotlbentry->attrs);

    if (r != MEMTX_OK) {

        cpu_transaction_failed(cpu, physaddr, addr, size, MMU_DATA_LOAD,

                               mmu_idx, iotlbentry->attrs, r, retaddr);

    }

    if (locked) {

        qemu_mutex_unlock_iothread();

    }
@@ -776,6 +783,7 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, 
}



static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry,

                      int mmu_idx,

                      uint64_t val, target_ulong addr,

                      uintptr_t retaddr, int size)

{
@@ -783,6 +791,7 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry, 
    hwaddr physaddr = iotlbentry->addr;

    MemoryRegion *mr = iotlb_to_region(cpu, physaddr, iotlbentry->attrs);

    bool locked = false;

    MemTxResult r;



    physaddr = (physaddr & TARGET_PAGE_MASK) + addr;

    if (mr != &io_mem_rom && mr != &io_mem_notdirty && !cpu->can_do_io) {
@@ -795,7 +804,12 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry, 
        qemu_mutex_lock_iothread();

        locked = true;

    }

    memory_region_dispatch_write(mr, physaddr, val, size, iotlbentry->attrs);

    r = memory_region_dispatch_write(mr, physaddr,

                                     val, size, iotlbentry->attrs);

    if (r != MEMTX_OK) {

        cpu_transaction_failed(cpu, physaddr, addr, size, MMU_DATA_STORE,

                               mmu_idx, iotlbentry->attrs, r, retaddr);

    }

    if (locked) {

        qemu_mutex_unlock_iothread();

    }
@@ -845,6 +859,7 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env, target_ulong addr) 
    MemoryRegion *mr;

    CPUState *cpu = ENV_GET_CPU(env);

    CPUIOTLBEntry *iotlbentry;

    hwaddr physaddr;



    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);

    mmu_idx = cpu_mmu_index(env, true);
@@ -868,6 +883,19 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env, target_ulong addr) 
        }

        qemu_mutex_unlock_iothread();



        /* Give the new-style cpu_transaction_failed() hook first chance

         * to handle this.

         * This is not the ideal place to detect and generate CPU

         * exceptions for instruction fetch failure (for instance

         * we don't know the length of the access that the CPU would

         * use, and it would be better to go ahead and try the access

         * and use the MemTXResult it produced). However it is the

         * simplest place we have currently available for the check.

         */

        physaddr = (iotlbentry->addr & TARGET_PAGE_MASK) + addr;

        cpu_transaction_failed(cpu, physaddr, addr, 0, MMU_INST_FETCH, mmu_idx,

                               iotlbentry->attrs, MEMTX_DECODE_ERROR, 0);



        cpu_unassigned_access(cpu, addr, false, true, 0, 4);

        /* The CPU's unassigned access hook might have longjumped out

         * with an exception. If it didn't (or there was no hook) then

hw/arm/armv7m.c

+2 −2
Original line number Diff line number Diff line
@@ -146,7 +146,7 @@ static void armv7m_instance_init(Object *obj) 
                             &error_abort);

    memory_region_init(&s->container, obj, "armv7m-container", UINT64_MAX);



    object_initialize(&s->nvic, sizeof(s->nvic), "armv7m_nvic");

    object_initialize(&s->nvic, sizeof(s->nvic), TYPE_NVIC);

    qdev_set_parent_bus(DEVICE(&s->nvic), sysbus_get_default());

    object_property_add_alias(obj, "num-irq",

                              OBJECT(&s->nvic), "num-irq", &error_abort);
@@ -293,7 +293,7 @@ DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq, 
        cpu_model = "cortex-m3";

    }



    armv7m = qdev_create(NULL, "armv7m");

    armv7m = qdev_create(NULL, TYPE_ARMV7M);

    qdev_prop_set_uint32(armv7m, "num-irq", num_irq);

    qdev_prop_set_string(armv7m, "cpu-model", cpu_model);

    object_property_set_link(OBJECT(armv7m), OBJECT(get_system_memory()),

hw/arm/aspeed_soc.c

+4 −0
Original line number Diff line number Diff line
@@ -183,6 +183,8 @@ static void aspeed_soc_init(Object *obj) 
        object_initialize(&s->wdt[i], sizeof(s->wdt[i]), TYPE_ASPEED_WDT);

        object_property_add_child(obj, "wdt[*]", OBJECT(&s->wdt[i]), NULL);

        qdev_set_parent_bus(DEVICE(&s->wdt[i]), sysbus_get_default());

        qdev_prop_set_uint32(DEVICE(&s->wdt[i]), "silicon-rev",

                                    sc->info->silicon_rev);

    }



    object_initialize(&s->ftgmac100, sizeof(s->ftgmac100), TYPE_FTGMAC100);
@@ -338,6 +340,8 @@ static void aspeed_soc_class_init(ObjectClass *oc, void *data) 


    sc->info = (AspeedSoCInfo *) data;

    dc->realize = aspeed_soc_realize;

    /* Reason: Uses serial_hds and nd_table in realize() directly */

    dc->user_creatable = false;

}



static const TypeInfo aspeed_soc_type_info = {

hw/arm/digic.c

+2 −0
Original line number Diff line number Diff line
@@ -101,6 +101,8 @@ static void digic_class_init(ObjectClass *oc, void *data) 
    DeviceClass *dc = DEVICE_CLASS(oc);



    dc->realize = digic_realize;

    /* Reason: Uses serial_hds in the realize function --> not usable twice */

    dc->user_creatable = false;

}



static const TypeInfo digic_type_info = {

hw/arm/exynos4210.c

+2 −2
Original line number Diff line number Diff line
@@ -33,7 +33,7 @@ 
#include "hw/arm/arm.h"

#include "hw/loader.h"

#include "hw/arm/exynos4210.h"

#include "hw/sd/sd.h"

#include "hw/sd/sdhci.h"

#include "hw/usb/hcd-ehci.h"



#define EXYNOS4210_CHIPID_ADDR         0x10000000
@@ -381,7 +381,7 @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem) 
        BlockBackend *blk;

        DriveInfo *di;



        dev = qdev_create(NULL, "generic-sdhci");

        dev = qdev_create(NULL, TYPE_SYSBUS_SDHCI);

        qdev_prop_set_uint32(dev, "capareg", EXYNOS4210_SDHCI_CAPABILITIES);

        qdev_init_nofail(dev);