Commit 2aeba0d0 authored by Julia Suvorova's avatar Julia Suvorova Committed by Peter Maydell
Browse files

target/arm: Strict alignment for ARMv6-M and ARMv8-M Baseline 



Unlike ARMv7-M, ARMv6-M and ARMv8-M Baseline only supports naturally
aligned memory accesses for load/store instructions.

Signed-off-by: default avatarJulia Suvorova <jusual@mail.ru>
Message-id: 20180622080138.17702-3-jusual@mail.ru
Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent cc2ae7c9

target/arm/translate.c

+16 −2
Original line number Diff line number Diff line
@@ -1100,7 +1100,14 @@ static inline TCGv gen_aa32_addr(DisasContext *s, TCGv_i32 a32, TCGMemOp op) 
static void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,

                            int index, TCGMemOp opc)

{

    TCGv addr = gen_aa32_addr(s, a32, opc);

    TCGv addr;



    if (arm_dc_feature(s, ARM_FEATURE_M) &&

        !arm_dc_feature(s, ARM_FEATURE_M_MAIN)) {

        opc |= MO_ALIGN;

    }



    addr = gen_aa32_addr(s, a32, opc);

    tcg_gen_qemu_ld_i32(val, addr, index, opc);

    tcg_temp_free(addr);

}
@@ -1108,7 +1115,14 @@ static void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, 
static void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,

                            int index, TCGMemOp opc)

{

    TCGv addr = gen_aa32_addr(s, a32, opc);

    TCGv addr;



    if (arm_dc_feature(s, ARM_FEATURE_M) &&

        !arm_dc_feature(s, ARM_FEATURE_M_MAIN)) {

        opc |= MO_ALIGN;

    }



    addr = gen_aa32_addr(s, a32, opc);

    tcg_gen_qemu_st_i32(val, addr, index, opc);

    tcg_temp_free(addr);

}