Commit 2aa09da8 authored by Anthony Liguori's avatar Anthony Liguori
Browse files

Merge remote-tracking branch 'origin/master' into staging 



* origin/master:
  mips: revert commit b332d24a
  tcg/mips: fix invalid op definition errors

Necessary because patches got pushed by Aurelien before I pushed
the -rc2 tag.

Signed-off-by: default avatarAnthony Liguori <aliguori@us.ibm.com>
parents 9b9734ef 2e985fe0

hw/mips/mips_fulong2e.c

+3 −1
Original line number Diff line number Diff line
@@ -44,6 +44,7 @@ 
#include "sysemu/blockdev.h"

#include "exec/address-spaces.h"

#include "sysemu/qtest.h"

#include "qemu/error-report.h"



#define DEBUG_FULONG2E_INIT
@@ -335,7 +336,8 @@ static void mips_fulong2e_init(QEMUMachineInitArgs *args) 


        if ((bios_size < 0 || bios_size > BIOS_SIZE) &&

            !kernel_filename && !qtest_enabled()) {

            fprintf(stderr, "qemu: Warning, could not load MIPS bios '%s'\n", bios_name);

            error_report("Could not load MIPS bios '%s'", bios_name);

            exit(1);

        }

    }

hw/mips/mips_jazz.c

+3 −2
Original line number Diff line number Diff line
@@ -43,6 +43,7 @@ 
#include "hw/sysbus.h"

#include "exec/address-spaces.h"

#include "sysemu/qtest.h"

#include "qemu/error-report.h"



enum jazz_model_e

{
@@ -178,8 +179,8 @@ static void mips_jazz_init(MemoryRegion *address_space, 
        bios_size = -1;

    }

    if ((bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) && !qtest_enabled()) {

        fprintf(stderr, "qemu: Warning, could not load MIPS bios '%s'\n",

                bios_name);

        error_report("Could not load MIPS bios '%s'", bios_name);

        exit(1);

    }



    /* Init CPU internal devices */

hw/mips/mips_malta.c

+4 −3
Original line number Diff line number Diff line
@@ -49,6 +49,7 @@ 
#include "hw/sysbus.h"             /* SysBusDevice */

#include "qemu/host-utils.h"

#include "sysemu/qtest.h"

#include "qemu/error-report.h"



//#define DEBUG_BOARD_INIT
@@ -1008,9 +1009,9 @@ void mips_malta_init(QEMUMachineInitArgs *args) 
            }

            if ((bios_size < 0 || bios_size > BIOS_SIZE) &&

                !kernel_filename && !qtest_enabled()) {

                fprintf(stderr,

                        "qemu: Warning, could not load MIPS bios '%s', and no -kernel argument was specified\n",

                        bios_name);

                error_report("Could not load MIPS bios '%s', and no "

                             "-kernel argument was specified", bios_name);

                exit(1);

            }

        }

        /* In little endian mode the 32bit words in the bios are swapped,

hw/mips/mips_mipssim.c

+4 −3
Original line number Diff line number Diff line
@@ -37,6 +37,7 @@ 
#include "elf.h"

#include "hw/sysbus.h"

#include "exec/address-spaces.h"

#include "qemu/error-report.h"



static struct _loaderparams {

    int ram_size;
@@ -191,9 +192,9 @@ mips_mipssim_init(QEMUMachineInitArgs *args) 
    }

    if ((bios_size < 0 || bios_size > BIOS_SIZE) && !kernel_filename) {

        /* Bail out if we have neither a kernel image nor boot vector code. */

        fprintf(stderr,

                "qemu: Warning, could not load MIPS bios '%s', and no -kernel argument was specified\n",

                filename);

        error_report("Could not load MIPS bios '%s', and no "

                     "-kernel argument was specified", filename);

        exit(1);

    } else {

        /* We have a boot vector start address. */

        env->active_tc.PC = (target_long)(int32_t)0xbfc00000;

tcg/mips/tcg-target.c

+10 −0
Original line number Diff line number Diff line
@@ -1617,19 +1617,29 @@ static const TCGTargetOpDef mips_op_defs[] = { 
    { INDEX_op_shl_i32, { "r", "rZ", "ri" } },

    { INDEX_op_shr_i32, { "r", "rZ", "ri" } },

    { INDEX_op_sar_i32, { "r", "rZ", "ri" } },

#if TCG_TARGET_HAS_rot_i32

    { INDEX_op_rotr_i32, { "r", "rZ", "ri" } },

    { INDEX_op_rotl_i32, { "r", "rZ", "ri" } },

#endif



#if TCG_TARGET_HAS_bswap16_i32

    { INDEX_op_bswap16_i32, { "r", "r" } },

#endif

#if TCG_TARGET_HAS_bswap32_i32

    { INDEX_op_bswap32_i32, { "r", "r" } },

#endif



    { INDEX_op_ext8s_i32, { "r", "rZ" } },

    { INDEX_op_ext16s_i32, { "r", "rZ" } },



#if TCG_TARGET_HAS_deposit_i32

    { INDEX_op_deposit_i32, { "r", "0", "rZ" } },

#endif



    { INDEX_op_brcond_i32, { "rZ", "rZ" } },

#if TCG_TARGET_HAS_movcond_i32

    { INDEX_op_movcond_i32, { "r", "rZ", "rZ", "rZ", "0" } },

#endif

    { INDEX_op_setcond_i32, { "r", "rZ", "rZ" } },

    { INDEX_op_setcond2_i32, { "r", "rZ", "rZ", "rZ", "rZ" } },