Commit 2a221651 authored by Edgar E. Iglesias's avatar Edgar E. Iglesias
Browse files

exec: Make cpu_physical_memory_write_rom input an AS 



Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: default avatarEdgar E. Iglesias <edgar.iglesias@xilinx.com>
parent db3be60d

exec.c

+8 −7
Original line number Diff line number Diff line
@@ -2102,7 +2102,7 @@ enum write_rom_type { 
    FLUSH_CACHE,

};



static inline void cpu_physical_memory_write_rom_internal(

static inline void cpu_physical_memory_write_rom_internal(AddressSpace *as,

    hwaddr addr, const uint8_t *buf, int len, enum write_rom_type type)

{

    hwaddr l;
@@ -2112,8 +2112,7 @@ static inline void cpu_physical_memory_write_rom_internal( 


    while (len > 0) {

        l = len;

        mr = address_space_translate(&address_space_memory,

                                     addr, &addr1, &l, true);

        mr = address_space_translate(as, addr, &addr1, &l, true);



        if (!(memory_region_is_ram(mr) ||

              memory_region_is_romd(mr))) {
@@ -2139,10 +2138,10 @@ static inline void cpu_physical_memory_write_rom_internal( 
}



/* used for ROM loading : can write in RAM and ROM */

void cpu_physical_memory_write_rom(hwaddr addr,

void cpu_physical_memory_write_rom(AddressSpace *as, hwaddr addr,

                                   const uint8_t *buf, int len)

{

    cpu_physical_memory_write_rom_internal(addr, buf, len, WRITE_DATA);

    cpu_physical_memory_write_rom_internal(as, addr, buf, len, WRITE_DATA);

}



void cpu_flush_icache_range(hwaddr start, int len)
@@ -2157,7 +2156,8 @@ void cpu_flush_icache_range(hwaddr start, int len) 
        return;

    }



    cpu_physical_memory_write_rom_internal(start, NULL, len, FLUSH_CACHE);

    cpu_physical_memory_write_rom_internal(&address_space_memory,

                                           start, NULL, len, FLUSH_CACHE);

}



typedef struct {
@@ -2721,7 +2721,8 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr, 
            l = len;

        phys_addr += (addr & ~TARGET_PAGE_MASK);

        if (is_write)

            cpu_physical_memory_write_rom(phys_addr, buf, l);

            cpu_physical_memory_write_rom(&address_space_memory,

                                          phys_addr, buf, l);

        else

            cpu_physical_memory_rw(phys_addr, buf, l, is_write);

        len -= l;

hw/core/loader.c

+2 −1
Original line number Diff line number Diff line
@@ -778,7 +778,8 @@ static void rom_reset(void *unused) 
            void *host = memory_region_get_ram_ptr(rom->mr);

            memcpy(host, rom->data, rom->datasize);

        } else {

            cpu_physical_memory_write_rom(rom->addr, rom->data, rom->datasize);

            cpu_physical_memory_write_rom(&address_space_memory,

                                          rom->addr, rom->data, rom->datasize);

        }

        if (rom->isrom) {

            /* rom needs to be written only once */

hw/intc/apic.c

+2 −1
Original line number Diff line number Diff line
@@ -129,7 +129,8 @@ static void apic_sync_vapic(APICCommonState *s, int sync_type) 
        }

        vapic_state.irr = vector & 0xff;



        cpu_physical_memory_write_rom(s->vapic_paddr + start,

        cpu_physical_memory_write_rom(&address_space_memory,

                                      s->vapic_paddr + start,

                                      ((void *)&vapic_state) + start, length);

    }

}

hw/sparc/sun4m.c

+2 −1
Original line number Diff line number Diff line
@@ -577,7 +577,8 @@ static void idreg_init(hwaddr addr) 
    s = SYS_BUS_DEVICE(dev);



    sysbus_mmio_map(s, 0, addr);

    cpu_physical_memory_write_rom(addr, idreg_data, sizeof(idreg_data));

    cpu_physical_memory_write_rom(&address_space_memory,

                                  addr, idreg_data, sizeof(idreg_data));

}



#define MACIO_ID_REGISTER(obj) \

include/exec/cpu-common.h

+1 −1
Original line number Diff line number Diff line
@@ -108,7 +108,7 @@ void stl_phys(AddressSpace *as, hwaddr addr, uint32_t val); 
void stq_phys(AddressSpace *as, hwaddr addr, uint64_t val);

#endif



void cpu_physical_memory_write_rom(hwaddr addr,

void cpu_physical_memory_write_rom(AddressSpace *as, hwaddr addr,

                                   const uint8_t *buf, int len);

void cpu_flush_icache_range(hwaddr start, int len);