Commit 29b8bcf1 authored by David Hildenbrand's avatar David Hildenbrand Committed by Cornelia Huck
Browse files

s390x/tcg: Implement VECTOR STORE MULTIPLE 



Similar to VECTOR LOAD MULTIPLE, just the opposite direction. Probe
write access first.

Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Signed-off-by: default avatarDavid Hildenbrand <david@redhat.com>
Message-Id: <20190307121539.12842-31-david@redhat.com>
Signed-off-by: default avatarCornelia Huck <cohuck@redhat.com>
parent 7b9a236e

target/s390x/insn-data.def

+2 −0
Original line number Diff line number Diff line
@@ -1041,6 +1041,8 @@ 
    E(0xe709, VSTEH,   VRX,   V,   la2, 0, 0, 0, vste, 0, ES_16, IF_VEC)

    E(0xe70b, VSTEF,   VRX,   V,   la2, 0, 0, 0, vste, 0, ES_32, IF_VEC)

    E(0xe70a, VSTEG,   VRX,   V,   la2, 0, 0, 0, vste, 0, ES_64, IF_VEC)

/* VECTOR STORE MULTIPLE */

    F(0xe73e, VSTM,    VRS_a, V,   la2, 0, 0, 0, vstm, 0, IF_VEC)



#ifndef CONFIG_USER_ONLY

/* COMPARE AND SWAP AND PURGE */

target/s390x/translate_vx.inc.c

+30 −0
Original line number Diff line number Diff line
@@ -852,3 +852,33 @@ static DisasJumpType op_vste(DisasContext *s, DisasOps *o) 
    tcg_temp_free_i64(tmp);

    return DISAS_NEXT;

}



static DisasJumpType op_vstm(DisasContext *s, DisasOps *o)

{

    const uint8_t v3 = get_field(s->fields, v3);

    uint8_t v1 = get_field(s->fields, v1);

    TCGv_i64 tmp;



    while (v3 < v1 || (v3 - v1 + 1) > 16) {

        gen_program_exception(s, PGM_SPECIFICATION);

        return DISAS_NORETURN;

    }



    /* Probe write access before actually modifying memory */

    tmp = tcg_const_i64((v3 - v1 + 1) * 16);

    gen_helper_probe_write_access(cpu_env, o->addr1, tmp);



    for (;; v1++) {

        read_vec_element_i64(tmp, v1, 0, ES_64);

        tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TEQ);

        gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8);

        read_vec_element_i64(tmp, v1, 1, ES_64);

        tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TEQ);

        if (v1 == v3) {

            break;

        }

        gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8);

    }

    tcg_temp_free_i64(tmp);

    return DISAS_NEXT;

}