Commit 29b80469 authored by Richard Henderson's avatar Richard Henderson Committed by Peter Maydell
Browse files

target/arm: Implement SVE Floating Point Arithmetic - Unpredicated Group 



Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Message-id: 20180613015641.5667-19-richard.henderson@linaro.org
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent 6e6a157d

target/arm/helper-sve.h

+14 −0
Original line number Diff line number Diff line
@@ -705,3 +705,17 @@ DEF_HELPER_FLAGS_4(sve_umini_b, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) 
DEF_HELPER_FLAGS_4(sve_umini_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)

DEF_HELPER_FLAGS_4(sve_umini_s, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)

DEF_HELPER_FLAGS_4(sve_umini_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)



DEF_HELPER_FLAGS_5(gvec_recps_h, TCG_CALL_NO_RWG,

                   void, ptr, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_5(gvec_recps_s, TCG_CALL_NO_RWG,

                   void, ptr, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_5(gvec_recps_d, TCG_CALL_NO_RWG,

                   void, ptr, ptr, ptr, ptr, i32)



DEF_HELPER_FLAGS_5(gvec_rsqrts_h, TCG_CALL_NO_RWG,

                   void, ptr, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_5(gvec_rsqrts_s, TCG_CALL_NO_RWG,

                   void, ptr, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_5(gvec_rsqrts_d, TCG_CALL_NO_RWG,

                   void, ptr, ptr, ptr, ptr, i32)

target/arm/helper.h

+19 −0
Original line number Diff line number Diff line
@@ -601,6 +601,25 @@ DEF_HELPER_FLAGS_5(gvec_fcmlas_idx, TCG_CALL_NO_RWG, 
DEF_HELPER_FLAGS_5(gvec_fcmlad, TCG_CALL_NO_RWG,

                   void, ptr, ptr, ptr, ptr, i32)



DEF_HELPER_FLAGS_5(gvec_fadd_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_5(gvec_fadd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_5(gvec_fadd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)



DEF_HELPER_FLAGS_5(gvec_fsub_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_5(gvec_fsub_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_5(gvec_fsub_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)



DEF_HELPER_FLAGS_5(gvec_fmul_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_5(gvec_fmul_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_5(gvec_fmul_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)



DEF_HELPER_FLAGS_5(gvec_ftsmul_h, TCG_CALL_NO_RWG,

                   void, ptr, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_5(gvec_ftsmul_s, TCG_CALL_NO_RWG,

                   void, ptr, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_5(gvec_ftsmul_d, TCG_CALL_NO_RWG,

                   void, ptr, ptr, ptr, ptr, i32)



#ifdef TARGET_AARCH64

#include "helper-a64.h"

#include "helper-sve.h"

target/arm/sve.decode

+10 −0
Original line number Diff line number Diff line
@@ -648,6 +648,16 @@ UMIN_zzi 00100101 .. 101 011 110 ........ ..... @rdn_i8u 
# SVE integer multiply immediate (unpredicated)

MUL_zzi         00100101 .. 110 000 110 ........ .....          @rdn_i8s



### SVE Floating Point Arithmetic - Unpredicated Group



# SVE floating-point arithmetic (unpredicated)

FADD_zzz        01100101 .. 0 ..... 000 000 ..... .....         @rd_rn_rm

FSUB_zzz        01100101 .. 0 ..... 000 001 ..... .....         @rd_rn_rm

FMUL_zzz        01100101 .. 0 ..... 000 010 ..... .....         @rd_rn_rm

FTSMUL          01100101 .. 0 ..... 000 011 ..... .....         @rd_rn_rm

FRECPS          01100101 .. 0 ..... 000 110 ..... .....         @rd_rn_rm

FRSQRTS         01100101 .. 0 ..... 000 111 ..... .....         @rd_rn_rm



### SVE Memory - 32-bit Gather and Unsized Contiguous Group



# SVE load predicate register

target/arm/translate-sve.c

+42 −0
Original line number Diff line number Diff line
@@ -3372,6 +3372,48 @@ DO_ZZI(UMIN, umin) 


#undef DO_ZZI



/*

 *** SVE Floating Point Arithmetic - Unpredicated Group

 */



static bool do_zzz_fp(DisasContext *s, arg_rrr_esz *a,

                      gen_helper_gvec_3_ptr *fn)

{

    if (fn == NULL) {

        return false;

    }

    if (sve_access_check(s)) {

        unsigned vsz = vec_full_reg_size(s);

        TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_16);

        tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd),

                           vec_full_reg_offset(s, a->rn),

                           vec_full_reg_offset(s, a->rm),

                           status, vsz, vsz, 0, fn);

        tcg_temp_free_ptr(status);

    }

    return true;

}





#define DO_FP3(NAME, name) \

static bool trans_##NAME(DisasContext *s, arg_rrr_esz *a, uint32_t insn) \

{                                                                   \

    static gen_helper_gvec_3_ptr * const fns[4] = {                 \

        NULL, gen_helper_gvec_##name##_h,                           \

        gen_helper_gvec_##name##_s, gen_helper_gvec_##name##_d      \

    };                                                              \

    return do_zzz_fp(s, a, fns[a->esz]);                            \

}



DO_FP3(FADD_zzz, fadd)

DO_FP3(FSUB_zzz, fsub)

DO_FP3(FMUL_zzz, fmul)

DO_FP3(FTSMUL, ftsmul)

DO_FP3(FRECPS, recps)

DO_FP3(FRSQRTS, rsqrts)



#undef DO_FP3



/*

 *** SVE Memory - 32-bit Gather and Unsized Contiguous Group

 */

target/arm/vec_helper.c

+69 −0
Original line number Diff line number Diff line
@@ -426,3 +426,72 @@ void HELPER(gvec_fcmlad)(void *vd, void *vn, void *vm, 
    }

    clear_tail(d, opr_sz, simd_maxsz(desc));

}



/* Floating-point trigonometric starting value.

 * See the ARM ARM pseudocode function FPTrigSMul.

 */

static float16 float16_ftsmul(float16 op1, uint16_t op2, float_status *stat)

{

    float16 result = float16_mul(op1, op1, stat);

    if (!float16_is_any_nan(result)) {

        result = float16_set_sign(result, op2 & 1);

    }

    return result;

}



static float32 float32_ftsmul(float32 op1, uint32_t op2, float_status *stat)

{

    float32 result = float32_mul(op1, op1, stat);

    if (!float32_is_any_nan(result)) {

        result = float32_set_sign(result, op2 & 1);

    }

    return result;

}



static float64 float64_ftsmul(float64 op1, uint64_t op2, float_status *stat)

{

    float64 result = float64_mul(op1, op1, stat);

    if (!float64_is_any_nan(result)) {

        result = float64_set_sign(result, op2 & 1);

    }

    return result;

}



#define DO_3OP(NAME, FUNC, TYPE) \

void HELPER(NAME)(void *vd, void *vn, void *vm, void *stat, uint32_t desc) \

{                                                                          \

    intptr_t i, oprsz = simd_oprsz(desc);                                  \

    TYPE *d = vd, *n = vn, *m = vm;                                        \

    for (i = 0; i < oprsz / sizeof(TYPE); i++) {                           \

        d[i] = FUNC(n[i], m[i], stat);                                     \

    }                                                                      \

}



DO_3OP(gvec_fadd_h, float16_add, float16)

DO_3OP(gvec_fadd_s, float32_add, float32)

DO_3OP(gvec_fadd_d, float64_add, float64)



DO_3OP(gvec_fsub_h, float16_sub, float16)

DO_3OP(gvec_fsub_s, float32_sub, float32)

DO_3OP(gvec_fsub_d, float64_sub, float64)



DO_3OP(gvec_fmul_h, float16_mul, float16)

DO_3OP(gvec_fmul_s, float32_mul, float32)

DO_3OP(gvec_fmul_d, float64_mul, float64)



DO_3OP(gvec_ftsmul_h, float16_ftsmul, float16)

DO_3OP(gvec_ftsmul_s, float32_ftsmul, float32)

DO_3OP(gvec_ftsmul_d, float64_ftsmul, float64)



#ifdef TARGET_AARCH64



DO_3OP(gvec_recps_h, helper_recpsf_f16, float16)

DO_3OP(gvec_recps_s, helper_recpsf_f32, float32)

DO_3OP(gvec_recps_d, helper_recpsf_f64, float64)



DO_3OP(gvec_rsqrts_h, helper_rsqrtsf_f16, float16)

DO_3OP(gvec_rsqrts_s, helper_rsqrtsf_f32, float32)

DO_3OP(gvec_rsqrts_d, helper_rsqrtsf_f64, float64)



#endif

#undef DO_3OP