Commit 298fae38 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20150907' into staging 



target-arm queue:
 * cleanup to use g_new() and friends
 * support semihosting in A64
 * add SMBIOS support to mach-virt
 * remove hw_error() usages
 * fix bug in the AArch32:AArch64 register mapping
 * add a second PCI memory window in highmem on virt board
 * fix bug in arm_excp_unmasked()
 * add i.MX31 SoC
 * remove restriction on handling affinity values in virt board

# gpg: Signature made Mon 07 Sep 2015 10:40:48 BST using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>"
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"

* remotes/pmaydell/tags/pull-target-arm-20150907: (27 commits)
  arm/virt: Add full-sized CPU affinity handling
  target-arm: Refactor CPU affinity handling
  i.MX: Add i2C devices to i.MX31 SOC
  i.MX: Add qtest support for I2C device emulator.
  i.MX: Add the i.MX25 PDK platform
  i.MX: Add SOC support for i.MX25
  i.MX: Add FEC Ethernet Emulator
  i.MX: Add I2C controller emulator
  i.MX: KZM: use standalone i.MX31 SOC support
  i.MX: Add SOC support for i.MX31
  target-arm: Fix arm_excp_unmasked() function
  hw/arm/virt: Add high MMIO PCI region, 512G in size
  target-arm: Fix AArch32:AArch64 general-purpose register mapping
  arm: Remove hw_error() usages.
  arm: cpu: assert() on no-EL2 virt IRQ error condition.
  smbios: implement smbios support for mach-virt
  smbios: add smbios 3.0 support
  target-arm: Wire up HLT 0xf000 as the A64 semihosting instruction
  target-arm/arm-semi.c: SYS_EXIT on A64 takes a parameter block
  target-arm/arm-semi.c: Implement A64 specific SyncCacheRange call
  ...

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents b597aa03 8d45c54d

default-configs/arm-softmmu.mak

+7 −0
Original line number Diff line number Diff line
@@ -28,6 +28,7 @@ CONFIG_SSI_M25P80=y 
CONFIG_LAN9118=y

CONFIG_SMC91C111=y

CONFIG_ALLWINNER_EMAC=y

CONFIG_IMX_FEC=y

CONFIG_DS1338=y

CONFIG_PFLASH_CFI01=y

CONFIG_PFLASH_CFI02=y
@@ -98,7 +99,13 @@ CONFIG_ALLWINNER_A10_PIT=y 
CONFIG_ALLWINNER_A10_PIC=y

CONFIG_ALLWINNER_A10=y



CONFIG_FSL_IMX31=y

CONFIG_FSL_IMX25=y



CONFIG_IMX_I2C=y



CONFIG_XIO3130=y

CONFIG_IOH3420=y

CONFIG_I82801B11=y

CONFIG_ACPI=y

CONFIG_SMBIOS=y

gdbstub.c

+10 −4
Original line number Diff line number Diff line
@@ -1301,9 +1301,8 @@ send_packet: 
    %x  - target_ulong argument printed in hex.

    %lx - 64-bit argument printed in hex.

    %s  - string pointer (target_ulong) and length (int) pair.  */

void gdb_do_syscall(gdb_syscall_complete_cb cb, const char *fmt, ...)

void gdb_do_syscallv(gdb_syscall_complete_cb cb, const char *fmt, va_list va)

{

    va_list va;

    char *p;

    char *p_end;

    target_ulong addr;
@@ -1317,7 +1316,6 @@ void gdb_do_syscall(gdb_syscall_complete_cb cb, const char *fmt, ...) 
#ifndef CONFIG_USER_ONLY

    vm_stop(RUN_STATE_DEBUG);

#endif

    va_start(va, fmt);

    p = s->syscall_buf;

    p_end = &s->syscall_buf[sizeof(s->syscall_buf)];

    *(p++) = 'F';
@@ -1351,7 +1349,6 @@ void gdb_do_syscall(gdb_syscall_complete_cb cb, const char *fmt, ...) 
        }

    }

    *p = 0;

    va_end(va);

#ifdef CONFIG_USER_ONLY

    put_packet(s, s->syscall_buf);

    gdb_handlesig(s->c_cpu, 0);
@@ -1366,6 +1363,15 @@ void gdb_do_syscall(gdb_syscall_complete_cb cb, const char *fmt, ...) 
#endif

}



void gdb_do_syscall(gdb_syscall_complete_cb cb, const char *fmt, ...)

{

    va_list va;



    va_start(va, fmt);

    gdb_do_syscallv(cb, fmt, va);

    va_end(va);

}



static void gdb_read_byte(GDBState *s, int ch)

{

    int i, csum;

hw/arm/Makefile.objs

+3 −1
Original line number Diff line number Diff line 
obj-y += boot.o collie.o exynos4_boards.o gumstix.o highbank.o

obj-$(CONFIG_DIGIC) += digic_boards.o

obj-y += integratorcp.o kzm.o mainstone.o musicpal.o nseries.o

obj-y += integratorcp.o mainstone.o musicpal.o nseries.o

obj-y += omap_sx1.o palm.o realview.o spitz.o stellaris.o

obj-y += tosa.o versatilepb.o vexpress.o virt.o xilinx_zynq.o z2.o

obj-$(CONFIG_ACPI) += virt-acpi-build.o
@@ -13,3 +13,5 @@ obj-y += omap1.o omap2.o strongarm.o 
obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o

obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o

obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-zynqmp.o xlnx-ep108.o

obj-$(CONFIG_FSL_IMX25) += fsl-imx25.o imx25_pdk.o

obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o

hw/arm/fsl-imx25.c

0 → 100644
+273 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2013 Jean-Christophe Dubois <jcd@tribudubois.net>

 *

 * i.MX25 SOC emulation.

 *

 * Based on hw/arm/xlnx-zynqmp.c

 *

 * Copyright (C) 2015 Xilinx Inc

 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>

 *

 *  This program is free software; you can redistribute it and/or modify it

 *  under the terms of the GNU General Public License as published by the

 *  Free Software Foundation; either version 2 of the License, or

 *  (at your option) any later version.

 *

 *  This program is distributed in the hope that it will be useful, but WITHOUT

 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License

 *  for more details.

 *

 *  You should have received a copy of the GNU General Public License along

 *  with this program; if not, see <http://www.gnu.org/licenses/>.

 */



#include "hw/arm/fsl-imx25.h"

#include "sysemu/sysemu.h"

#include "exec/address-spaces.h"

#include "hw/boards.h"

#include "sysemu/char.h"



static void fsl_imx25_init(Object *obj)

{

    FslIMX25State *s = FSL_IMX25(obj);

    int i;



    object_initialize(&s->cpu, sizeof(s->cpu), "arm926-" TYPE_ARM_CPU);



    object_initialize(&s->avic, sizeof(s->avic), TYPE_IMX_AVIC);

    qdev_set_parent_bus(DEVICE(&s->avic), sysbus_get_default());



    object_initialize(&s->ccm, sizeof(s->ccm), TYPE_IMX_CCM);

    qdev_set_parent_bus(DEVICE(&s->ccm), sysbus_get_default());



    for (i = 0; i < FSL_IMX25_NUM_UARTS; i++) {

        object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_IMX_SERIAL);

        qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default());

    }



    for (i = 0; i < FSL_IMX25_NUM_GPTS; i++) {

        object_initialize(&s->gpt[i], sizeof(s->gpt[i]), TYPE_IMX_GPT);

        qdev_set_parent_bus(DEVICE(&s->gpt[i]), sysbus_get_default());

    }



    for (i = 0; i < FSL_IMX25_NUM_EPITS; i++) {

        object_initialize(&s->epit[i], sizeof(s->epit[i]), TYPE_IMX_EPIT);

        qdev_set_parent_bus(DEVICE(&s->epit[i]), sysbus_get_default());

    }



    object_initialize(&s->fec, sizeof(s->fec), TYPE_IMX_FEC);

    qdev_set_parent_bus(DEVICE(&s->fec), sysbus_get_default());



    for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) {

        object_initialize(&s->i2c[i], sizeof(s->i2c[i]), TYPE_IMX_I2C);

        qdev_set_parent_bus(DEVICE(&s->i2c[i]), sysbus_get_default());

    }

}



static void fsl_imx25_realize(DeviceState *dev, Error **errp)

{

    FslIMX25State *s = FSL_IMX25(dev);

    uint8_t i;

    Error *err = NULL;



    object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);

    if (err) {

        error_propagate(errp, err);

        return;

    }



    object_property_set_bool(OBJECT(&s->avic), true, "realized", &err);

    if (err) {

        error_propagate(errp, err);

        return;

    }

    sysbus_mmio_map(SYS_BUS_DEVICE(&s->avic), 0, FSL_IMX25_AVIC_ADDR);

    sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 0,

                       qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));

    sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 1,

                       qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));



    object_property_set_bool(OBJECT(&s->ccm), true, "realized", &err);

    if (err) {

        error_propagate(errp, err);

        return;

    }

    sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX25_CCM_ADDR);



    /* Initialize all UARTs */

    for (i = 0; i < FSL_IMX25_NUM_UARTS; i++) {

        static const struct {

            hwaddr addr;

            unsigned int irq;

        } serial_table[FSL_IMX25_NUM_UARTS] = {

            { FSL_IMX25_UART1_ADDR, FSL_IMX25_UART1_IRQ },

            { FSL_IMX25_UART2_ADDR, FSL_IMX25_UART2_IRQ },

            { FSL_IMX25_UART3_ADDR, FSL_IMX25_UART3_IRQ },

            { FSL_IMX25_UART4_ADDR, FSL_IMX25_UART4_IRQ },

            { FSL_IMX25_UART5_ADDR, FSL_IMX25_UART5_IRQ }

        };



        if (i < MAX_SERIAL_PORTS) {

            CharDriverState *chr;



            chr = serial_hds[i];



            if (!chr) {

                char label[20];

                snprintf(label, sizeof(label), "imx31.uart%d", i);

                chr = qemu_chr_new(label, "null", NULL);

            }



            qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr);

        }



        object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);

        if (err) {

            error_propagate(errp, err);

            return;

        }

        sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr);

        sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,

                           qdev_get_gpio_in(DEVICE(&s->avic),

                                            serial_table[i].irq));

    }



    /* Initialize all GPT timers */

    for (i = 0; i < FSL_IMX25_NUM_GPTS; i++) {

        static const struct {

            hwaddr addr;

            unsigned int irq;

        } gpt_table[FSL_IMX25_NUM_GPTS] = {

            { FSL_IMX25_GPT1_ADDR, FSL_IMX25_GPT1_IRQ },

            { FSL_IMX25_GPT2_ADDR, FSL_IMX25_GPT2_IRQ },

            { FSL_IMX25_GPT3_ADDR, FSL_IMX25_GPT3_IRQ },

            { FSL_IMX25_GPT4_ADDR, FSL_IMX25_GPT4_IRQ }

        };



        s->gpt[i].ccm = DEVICE(&s->ccm);



        object_property_set_bool(OBJECT(&s->gpt[i]), true, "realized", &err);

        if (err) {

            error_propagate(errp, err);

            return;

        }

        sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, gpt_table[i].addr);

        sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0,

                           qdev_get_gpio_in(DEVICE(&s->avic),

                                            gpt_table[i].irq));

    }



    /* Initialize all EPIT timers */

    for (i = 0; i < FSL_IMX25_NUM_EPITS; i++) {

        static const struct {

            hwaddr addr;

            unsigned int irq;

        } epit_table[FSL_IMX25_NUM_EPITS] = {

            { FSL_IMX25_EPIT1_ADDR, FSL_IMX25_EPIT1_IRQ },

            { FSL_IMX25_EPIT2_ADDR, FSL_IMX25_EPIT2_IRQ }

        };



        s->epit[i].ccm = DEVICE(&s->ccm);



        object_property_set_bool(OBJECT(&s->epit[i]), true, "realized", &err);

        if (err) {

            error_propagate(errp, err);

            return;

        }

        sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr);

        sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,

                           qdev_get_gpio_in(DEVICE(&s->avic),

                                            epit_table[i].irq));

    }



    qdev_set_nic_properties(DEVICE(&s->fec), &nd_table[0]);

    object_property_set_bool(OBJECT(&s->fec), true, "realized", &err);

    if (err) {

        error_propagate(errp, err);

        return;

    }

    sysbus_mmio_map(SYS_BUS_DEVICE(&s->fec), 0, FSL_IMX25_FEC_ADDR);

    sysbus_connect_irq(SYS_BUS_DEVICE(&s->fec), 0,

                       qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX25_FEC_IRQ));





    /* Initialize all I2C */

    for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) {

        static const struct {

            hwaddr addr;

            unsigned int irq;

        } i2c_table[FSL_IMX25_NUM_I2CS] = {

            { FSL_IMX25_I2C1_ADDR, FSL_IMX25_I2C1_IRQ },

            { FSL_IMX25_I2C2_ADDR, FSL_IMX25_I2C2_IRQ },

            { FSL_IMX25_I2C3_ADDR, FSL_IMX25_I2C3_IRQ }

        };



        object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err);

        if (err) {

            error_propagate(errp, err);

            return;

        }

        sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr);

        sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,

                           qdev_get_gpio_in(DEVICE(&s->avic),

                                            i2c_table[i].irq));

    }



    /* initialize 2 x 16 KB ROM */

    memory_region_init_rom_device(&s->rom[0], NULL, NULL, NULL,

                                  "imx25.rom0", FSL_IMX25_ROM0_SIZE, &err);

    if (err) {

        error_propagate(errp, err);

        return;

    }

    memory_region_add_subregion(get_system_memory(), FSL_IMX25_ROM0_ADDR,

                                &s->rom[0]);

    memory_region_init_rom_device(&s->rom[1], NULL, NULL, NULL,

                                  "imx25.rom1", FSL_IMX25_ROM1_SIZE, &err);

    if (err) {

        error_propagate(errp, err);

        return;

    }

    memory_region_add_subregion(get_system_memory(), FSL_IMX25_ROM1_ADDR,

                                &s->rom[1]);



    /* initialize internal RAM (128 KB) */

    memory_region_init_ram(&s->iram, NULL, "imx25.iram", FSL_IMX25_IRAM_SIZE,

                           &err);

    if (err) {

        error_propagate(errp, err);

        return;

    }

    memory_region_add_subregion(get_system_memory(), FSL_IMX25_IRAM_ADDR,

                                &s->iram);

    vmstate_register_ram_global(&s->iram);



    /* internal RAM (128 KB) is aliased over 128 MB - 128 KB */

    memory_region_init_alias(&s->iram_alias, NULL, "imx25.iram_alias",

                             &s->iram, 0, FSL_IMX25_IRAM_ALIAS_SIZE);

    memory_region_add_subregion(get_system_memory(), FSL_IMX25_IRAM_ALIAS_ADDR,

                                &s->iram_alias);

}



static void fsl_imx25_class_init(ObjectClass *oc, void *data)

{

    DeviceClass *dc = DEVICE_CLASS(oc);



    dc->realize = fsl_imx25_realize;

}



static const TypeInfo fsl_imx25_type_info = {

    .name = TYPE_FSL_IMX25,

    .parent = TYPE_DEVICE,

    .instance_size = sizeof(FslIMX25State),

    .instance_init = fsl_imx25_init,

    .class_init = fsl_imx25_class_init,

};



static void fsl_imx25_register_types(void)

{

    type_register_static(&fsl_imx25_type_info);

}



type_init(fsl_imx25_register_types)

hw/arm/fsl-imx31.c

0 → 100644
+246 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2013 Jean-Christophe Dubois <jcd@tribudubois.net>

 *

 * i.MX31 SOC emulation.

 *

 * Based on hw/arm/fsl-imx31.c

 *

 *  This program is free software; you can redistribute it and/or modify it

 *  under the terms of the GNU General Public License as published by the

 *  Free Software Foundation; either version 2 of the License, or

 *  (at your option) any later version.

 *

 *  This program is distributed in the hope that it will be useful, but WITHOUT

 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License

 *  for more details.

 *

 *  You should have received a copy of the GNU General Public License along

 *  with this program; if not, see <http://www.gnu.org/licenses/>.

 */



#include "hw/arm/fsl-imx31.h"

#include "sysemu/sysemu.h"

#include "exec/address-spaces.h"

#include "hw/boards.h"

#include "sysemu/char.h"



static void fsl_imx31_init(Object *obj)

{

    FslIMX31State *s = FSL_IMX31(obj);

    int i;



    object_initialize(&s->cpu, sizeof(s->cpu), "arm1136-" TYPE_ARM_CPU);



    object_initialize(&s->avic, sizeof(s->avic), TYPE_IMX_AVIC);

    qdev_set_parent_bus(DEVICE(&s->avic), sysbus_get_default());



    object_initialize(&s->ccm, sizeof(s->ccm), TYPE_IMX_CCM);

    qdev_set_parent_bus(DEVICE(&s->ccm), sysbus_get_default());



    for (i = 0; i < FSL_IMX31_NUM_UARTS; i++) {

        object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_IMX_SERIAL);

        qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default());

    }



    object_initialize(&s->gpt, sizeof(s->gpt), TYPE_IMX_GPT);

    qdev_set_parent_bus(DEVICE(&s->gpt), sysbus_get_default());



    for (i = 0; i < FSL_IMX31_NUM_EPITS; i++) {

        object_initialize(&s->epit[i], sizeof(s->epit[i]), TYPE_IMX_EPIT);

        qdev_set_parent_bus(DEVICE(&s->epit[i]), sysbus_get_default());

    }



    for (i = 0; i < FSL_IMX31_NUM_I2CS; i++) {

        object_initialize(&s->i2c[i], sizeof(s->i2c[i]), TYPE_IMX_I2C);

        qdev_set_parent_bus(DEVICE(&s->i2c[i]), sysbus_get_default());

    }

}



static void fsl_imx31_realize(DeviceState *dev, Error **errp)

{

    FslIMX31State *s = FSL_IMX31(dev);

    uint16_t i;

    Error *err = NULL;



    object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);

    if (err) {

        error_propagate(errp, err);

        return;

    }



    object_property_set_bool(OBJECT(&s->avic), true, "realized", &err);

    if (err) {

        error_propagate(errp, err);

        return;

    }

    sysbus_mmio_map(SYS_BUS_DEVICE(&s->avic), 0, FSL_IMX31_AVIC_ADDR);

    sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 0,

                       qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));

    sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 1,

                       qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));



    object_property_set_bool(OBJECT(&s->ccm), true, "realized", &err);

    if (err) {

        error_propagate(errp, err);

        return;

    }

    sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX31_CCM_ADDR);



    /* Initialize all UARTS */

    for (i = 0; i < FSL_IMX31_NUM_UARTS; i++) {

        static const struct {

            hwaddr addr;

            unsigned int irq;

        } serial_table[FSL_IMX31_NUM_UARTS] = {

            { FSL_IMX31_UART1_ADDR, FSL_IMX31_UART1_IRQ },

            { FSL_IMX31_UART2_ADDR, FSL_IMX31_UART2_IRQ },

        };



        if (i < MAX_SERIAL_PORTS) {

            CharDriverState *chr;



            chr = serial_hds[i];



            if (!chr) {

                char label[20];

                snprintf(label, sizeof(label), "imx31.uart%d", i);

                chr = qemu_chr_new(label, "null", NULL);

            }



            qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr);

        }



        object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);

        if (err) {

            error_propagate(errp, err);

            return;

        }



        sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr);

        sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,

                           qdev_get_gpio_in(DEVICE(&s->avic),

                                            serial_table[i].irq));

    }



    s->gpt.ccm = DEVICE(&s->ccm);



    object_property_set_bool(OBJECT(&s->gpt), true, "realized", &err);

    if (err) {

        error_propagate(errp, err);

        return;

    }



    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt), 0, FSL_IMX31_GPT_ADDR);

    sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), 0,

                       qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX31_GPT_IRQ));



    /* Initialize all EPIT timers */

    for (i = 0; i < FSL_IMX31_NUM_EPITS; i++) {

        static const struct {

            hwaddr addr;

            unsigned int irq;

        } epit_table[FSL_IMX31_NUM_EPITS] = {

            { FSL_IMX31_EPIT1_ADDR, FSL_IMX31_EPIT1_IRQ },

            { FSL_IMX31_EPIT2_ADDR, FSL_IMX31_EPIT2_IRQ },

        };



        s->epit[i].ccm = DEVICE(&s->ccm);



        object_property_set_bool(OBJECT(&s->epit[i]), true, "realized", &err);

        if (err) {

            error_propagate(errp, err);

            return;

        }



        sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr);

        sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,

                           qdev_get_gpio_in(DEVICE(&s->avic),

                                            epit_table[i].irq));

    }



    /* Initialize all I2C */

    for (i = 0; i < FSL_IMX31_NUM_I2CS; i++) {

        static const struct {

            hwaddr addr;

            unsigned int irq;

        } i2c_table[FSL_IMX31_NUM_I2CS] = {

            { FSL_IMX31_I2C1_ADDR, FSL_IMX31_I2C1_IRQ },

            { FSL_IMX31_I2C2_ADDR, FSL_IMX31_I2C2_IRQ },

            { FSL_IMX31_I2C3_ADDR, FSL_IMX31_I2C3_IRQ }

        };



        /* Initialize the I2C */

        object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err);

        if (err) {

            error_propagate(errp, err);

            return;

        }

        /* Map I2C memory */

        sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr);

        /* Connect I2C IRQ to PIC */

        sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,

                           qdev_get_gpio_in(DEVICE(&s->avic),

                                            i2c_table[i].irq));

    }



    /* On a real system, the first 16k is a `secure boot rom' */

    memory_region_init_rom_device(&s->secure_rom, NULL, NULL, NULL,

                                  "imx31.secure_rom",

                                  FSL_IMX31_SECURE_ROM_SIZE, &err);

    if (err) {

        error_propagate(errp, err);

        return;

    }

    memory_region_add_subregion(get_system_memory(), FSL_IMX31_SECURE_ROM_ADDR,

                                &s->secure_rom);



    /* There is also a 16k ROM */

    memory_region_init_rom_device(&s->rom, NULL, NULL, NULL, "imx31.rom",

                                  FSL_IMX31_ROM_SIZE, &err);

    if (err) {

        error_propagate(errp, err);

        return;

    }

    memory_region_add_subregion(get_system_memory(), FSL_IMX31_ROM_ADDR,

                                &s->rom);



    /* initialize internal RAM (16 KB) */

    memory_region_init_ram(&s->iram, NULL, "imx31.iram", FSL_IMX31_IRAM_SIZE,

                           &err);

    if (err) {

        error_propagate(errp, err);

        return;

    }

    memory_region_add_subregion(get_system_memory(), FSL_IMX31_IRAM_ADDR,

                                &s->iram);

    vmstate_register_ram_global(&s->iram);



    /* internal RAM (16 KB) is aliased over 256 MB - 16 KB */

    memory_region_init_alias(&s->iram_alias, NULL, "imx31.iram_alias",

                             &s->iram, 0, FSL_IMX31_IRAM_ALIAS_SIZE);

    memory_region_add_subregion(get_system_memory(), FSL_IMX31_IRAM_ALIAS_ADDR,

                                &s->iram_alias);

}



static void fsl_imx31_class_init(ObjectClass *oc, void *data)

{

    DeviceClass *dc = DEVICE_CLASS(oc);



    dc->realize = fsl_imx31_realize;

}



static const TypeInfo fsl_imx31_type_info = {

    .name = TYPE_FSL_IMX31,

    .parent = TYPE_DEVICE,

    .instance_size = sizeof(FslIMX31State),

    .instance_init = fsl_imx31_init,

    .class_init = fsl_imx31_class_init,

};



static void fsl_imx31_register_types(void)

{

    type_register_static(&fsl_imx31_type_info);

}



type_init(fsl_imx31_register_types)