Commit 298b468e authored by Richard Henderson's avatar Richard Henderson
Browse files

fpu/softfloat: Introduce parts_is_snan_frac

parent 94933df0
Loading
Loading
Loading
Loading
+15 −0
Original line number Diff line number Diff line
@@ -86,6 +86,21 @@ this code that are retained.
#define NO_SIGNALING_NANS 1
#endif

/*----------------------------------------------------------------------------
| For the deconstructed floating-point with fraction FRAC, return true
| if the fraction represents a signalling NaN; otherwise false.
*----------------------------------------------------------------------------*/

static bool parts_is_snan_frac(uint64_t frac, float_status *status)
{
#ifdef NO_SIGNALING_NANS
    return false;
#else
    flag msb = extract64(frac, DECOMPOSED_BINARY_POINT - 1, 1);
    return msb == status->snan_bit_is_one;
#endif
}

/*----------------------------------------------------------------------------
| The pattern for a default generated half-precision NaN.
*----------------------------------------------------------------------------*/
+2 −10
Original line number Diff line number Diff line
@@ -331,16 +331,8 @@ static FloatParts canonicalize(FloatParts part, const FloatFmt *parm,
            part.cls = float_class_inf;
        } else {
            part.frac <<= parm->frac_shift;
#ifdef NO_SIGNALING_NANS
            part.cls = float_class_qnan;
#else
            int64_t msb = part.frac << 2;
            if ((msb < 0) == status->snan_bit_is_one) {
                part.cls = float_class_snan;
            } else {
                part.cls = float_class_qnan;
            }
#endif
            part.cls = (parts_is_snan_frac(part.frac, status)
                        ? float_class_snan : float_class_qnan);
        }
    } else if (part.exp == 0) {
        if (likely(part.frac == 0)) {