Loading hw/microblaze/petalogix_ml605_mmu.c +6 −1 Original line number Diff line number Diff line Loading @@ -134,7 +134,12 @@ petalogix_ml605_init(QEMUMachineInitArgs *args) DEVICE_LITTLE_ENDIAN); /* 2 timers at irq 2 @ 100 Mhz. */ xilinx_timer_create(TIMER_BASEADDR, irq[2], 0, 100 * 1000000); dev = qdev_create(NULL, "xlnx.xps-timer"); qdev_prop_set_uint32(dev, "one-timer-only", 0); qdev_prop_set_uint32(dev, "clock-frequency", 100 * 1000000); qdev_init_nofail(dev); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR); sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]); /* axi ethernet and dma initialization. */ qemu_check_nic_model(&nd_table[0], "xlnx.axi-ethernet"); Loading hw/microblaze/petalogix_s3adsp1800_mmu.c +8 −1 Original line number Diff line number Diff line Loading @@ -110,8 +110,15 @@ petalogix_s3adsp1800_init(QEMUMachineInitArgs *args) sysbus_create_simple("xlnx.xps-uartlite", UARTLITE_BASEADDR, irq[UARTLITE_IRQ]); /* 2 timers at irq 2 @ 62 Mhz. */ xilinx_timer_create(TIMER_BASEADDR, irq[0], 0, 62 * 1000000); dev = qdev_create(NULL, "xlnx.xps-timer"); qdev_prop_set_uint32(dev, "one-timer-only", 0); qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000); qdev_init_nofail(dev); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR); sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]); xilinx_ethlite_create(&nd_table[0], ETHLITE_BASEADDR, irq[1], 0, 0); microblaze_load_kernel(cpu, ddr_base, ram_size, Loading hw/ppc/virtex_ml507.c +6 −1 Original line number Diff line number Diff line Loading @@ -231,7 +231,12 @@ static void virtex_init(QEMUMachineInitArgs *args) 115200, serial_hds[0], DEVICE_LITTLE_ENDIAN); /* 2 timers at irq 2 @ 62 Mhz. */ xilinx_timer_create(0x83c00000, irq[3], 0, 62 * 1000000); dev = qdev_create(NULL, "xlnx.xps-timer"); qdev_prop_set_uint32(dev, "one-timer-only", 0); qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000); qdev_init_nofail(dev); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR); sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]); if (kernel_filename) { uint64_t entry, low, high; Loading include/hw/xilinx.h +0 −15 Original line number Diff line number Diff line Loading @@ -7,21 +7,6 @@ #include "hw/stream.h" #include "net/net.h" /* OPB Timer/Counter. */ static inline DeviceState * xilinx_timer_create(hwaddr base, qemu_irq irq, int oto, int freq) { DeviceState *dev; dev = qdev_create(NULL, "xlnx.xps-timer"); qdev_prop_set_uint32(dev, "one-timer-only", oto); qdev_prop_set_uint32(dev, "clock-frequency", freq); qdev_init_nofail(dev); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq); return dev; } /* XPS Ethernet Lite MAC. */ static inline DeviceState * xilinx_ethlite_create(NICInfo *nd, hwaddr base, qemu_irq irq, Loading Loading
hw/microblaze/petalogix_ml605_mmu.c +6 −1 Original line number Diff line number Diff line Loading @@ -134,7 +134,12 @@ petalogix_ml605_init(QEMUMachineInitArgs *args) DEVICE_LITTLE_ENDIAN); /* 2 timers at irq 2 @ 100 Mhz. */ xilinx_timer_create(TIMER_BASEADDR, irq[2], 0, 100 * 1000000); dev = qdev_create(NULL, "xlnx.xps-timer"); qdev_prop_set_uint32(dev, "one-timer-only", 0); qdev_prop_set_uint32(dev, "clock-frequency", 100 * 1000000); qdev_init_nofail(dev); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR); sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]); /* axi ethernet and dma initialization. */ qemu_check_nic_model(&nd_table[0], "xlnx.axi-ethernet"); Loading
hw/microblaze/petalogix_s3adsp1800_mmu.c +8 −1 Original line number Diff line number Diff line Loading @@ -110,8 +110,15 @@ petalogix_s3adsp1800_init(QEMUMachineInitArgs *args) sysbus_create_simple("xlnx.xps-uartlite", UARTLITE_BASEADDR, irq[UARTLITE_IRQ]); /* 2 timers at irq 2 @ 62 Mhz. */ xilinx_timer_create(TIMER_BASEADDR, irq[0], 0, 62 * 1000000); dev = qdev_create(NULL, "xlnx.xps-timer"); qdev_prop_set_uint32(dev, "one-timer-only", 0); qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000); qdev_init_nofail(dev); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR); sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]); xilinx_ethlite_create(&nd_table[0], ETHLITE_BASEADDR, irq[1], 0, 0); microblaze_load_kernel(cpu, ddr_base, ram_size, Loading
hw/ppc/virtex_ml507.c +6 −1 Original line number Diff line number Diff line Loading @@ -231,7 +231,12 @@ static void virtex_init(QEMUMachineInitArgs *args) 115200, serial_hds[0], DEVICE_LITTLE_ENDIAN); /* 2 timers at irq 2 @ 62 Mhz. */ xilinx_timer_create(0x83c00000, irq[3], 0, 62 * 1000000); dev = qdev_create(NULL, "xlnx.xps-timer"); qdev_prop_set_uint32(dev, "one-timer-only", 0); qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000); qdev_init_nofail(dev); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR); sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]); if (kernel_filename) { uint64_t entry, low, high; Loading
include/hw/xilinx.h +0 −15 Original line number Diff line number Diff line Loading @@ -7,21 +7,6 @@ #include "hw/stream.h" #include "net/net.h" /* OPB Timer/Counter. */ static inline DeviceState * xilinx_timer_create(hwaddr base, qemu_irq irq, int oto, int freq) { DeviceState *dev; dev = qdev_create(NULL, "xlnx.xps-timer"); qdev_prop_set_uint32(dev, "one-timer-only", oto); qdev_prop_set_uint32(dev, "clock-frequency", freq); qdev_init_nofail(dev); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq); return dev; } /* XPS Ethernet Lite MAC. */ static inline DeviceState * xilinx_ethlite_create(NICInfo *nd, hwaddr base, qemu_irq irq, Loading