Commit 29429c72 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20140929' into staging 



target-arm:
 * more EL2/EL3 preparation work
 * don't handle c15_cpar changes via tb_flush()
 * fix some unused function warnings in ARM devices
 * build the GDB XML for 32 bit CPUs into qemu-*-aarch64
 * implement guest breakpoint support

# gpg: Signature made Mon 29 Sep 2014 19:25:37 BST using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"

* remotes/pmaydell/tags/pull-target-arm-20140929:
  target-arm: Add support for VIRQ and VFIQ
  target-arm: Add IRQ and FIQ routing to EL2 and 3
  target-arm: A64: Emulate the SMC insn
  target-arm: Add a Hypervisor Trap exception type
  target-arm: A64: Emulate the HVC insn
  target-arm: A64: Correct updates to FAR and ESR on exceptions
  target-arm: Don't take interrupts targeting lower ELs
  target-arm: Break out exception masking to a separate func
  target-arm: A64: Refactor aarch64_cpu_do_interrupt
  target-arm: Add SCR_EL3
  target-arm: Add HCR_EL2
  target-arm: Don't handle c15_cpar changes via tb_flush()
  hw/input/tsc210x.c: Delete unused array tsc2101_rates
  hw/display/pxa2xx_lcd.c: Remove unused function pxa2xx_dma_rdst_set
  hw/intc/imx_avic.c: Remove unused function imx_avic_set_prio()
  hw/display/blizzard.c: Delete unused function blizzard_rgb2yuv
  configure: Build GDB XML for 32 bit ARM CPUs into qemu aarch64 binaries
  target-arm: Implement handling of breakpoint firing
  target-arm: Implement setting guest breakpoints

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 70d3a7a7 136e67e9

configure

+1 −1
Original line number Diff line number Diff line
@@ -5028,7 +5028,7 @@ case "$target_name" in 
  aarch64)

    TARGET_BASE_ARCH=arm

    bflt="yes"

    gdb_xml_files="aarch64-core.xml aarch64-fpu.xml"

    gdb_xml_files="aarch64-core.xml aarch64-fpu.xml arm-core.xml arm-vfp.xml arm-vfp3.xml arm-neon.xml"

  ;;

  cris)

  ;;

hw/display/blizzard.c

+0 −8
Original line number Diff line number Diff line
@@ -134,14 +134,6 @@ static const int blizzard_iformat_bpp[0x10] = { 
    0, 0, 0, 0, 0, 0,

};



static inline void blizzard_rgb2yuv(int r, int g, int b,

                int *y, int *u, int *v)

{

    *y = 0x10 + ((0x838 * r + 0x1022 * g + 0x322 * b) >> 13);

    *u = 0x80 + ((0xe0e * b - 0x04c1 * r - 0x94e * g) >> 13);

    *v = 0x80 + ((0xe0e * r - 0x0bc7 * g - 0x247 * b) >> 13);

}



static void blizzard_window(BlizzardState *s)

{

    DisplaySurface *surface = qemu_console_surface(s->con);

hw/display/pxa2xx_lcd.c

+0 −8
Original line number Diff line number Diff line
@@ -279,14 +279,6 @@ static inline void pxa2xx_dma_ber_set(PXA2xxLCDState *s, int ch) 
        s->liidr = s->dma_ch[ch].id;

}



/* Set Read Status interrupt high and poke associated registers */

static inline void pxa2xx_dma_rdst_set(PXA2xxLCDState *s)

{

    s->status[0] |= LCSR0_RDST;

    if (s->irqlevel && !(s->control[0] & LCCR0_RDSTM))

        s->status[0] |= LCSR0_SINT;

}



/* Load new Frame Descriptors from DMA */

static void pxa2xx_descriptor_load(PXA2xxLCDState *s)

{

hw/input/tsc210x.c

+0 −30
Original line number Diff line number Diff line
@@ -215,36 +215,6 @@ typedef struct { 
    int fsref;

} TSC210xRateInfo;



/*  { rate,  dsor,  fsref } */

static const TSC210xRateInfo tsc2101_rates[] = {

    /* Fsref / 6.0 */

    { 7350,	7,	1 },

    { 8000,	7,	0 },

    /* Fsref / 5.5 */

    { 8018,	6,	1 },

    { 8727,	6,	0 },

    /* Fsref / 5.0 */

    { 8820,	5,	1 },

    { 9600,	5,	0 },

    /* Fsref / 4.0 */

    { 11025,	4,	1 },

    { 12000,	4,	0 },

    /* Fsref / 3.0 */

    { 14700,	3,	1 },

    { 16000,	3,	0 },

    /* Fsref / 2.0 */

    { 22050,	2,	1 },

    { 24000,	2,	0 },

    /* Fsref / 1.5 */

    { 29400,	1,	1 },

    { 32000,	1,	0 },

    /* Fsref */

    { 44100,	0,	1 },

    { 48000,	0,	0 },



    { 0,	0, 	0 },

};



/*  { rate,   dsor, fsref }	*/

static const TSC210xRateInfo tsc2102_rates[] = {

    /* Fsref / 6.0 */

hw/intc/imx_avic.c

+0 −9
Original line number Diff line number Diff line
@@ -97,15 +97,6 @@ static inline int imx_avic_prio(IMXAVICState *s, int irq) 
    return 0xf & (s->prio[word] >> part);

}



static inline void imx_avic_set_prio(IMXAVICState *s, int irq, int prio)

{

    uint32_t word = irq / PRIO_PER_WORD;

    uint32_t part = 4 * (irq % PRIO_PER_WORD);

    uint32_t mask = ~(0xf << part);

    s->prio[word] &= mask;

    s->prio[word] |= prio << part;

}



/* Update interrupts.  */

static void imx_avic_update(IMXAVICState *s)

{