Loading hw/acpi_piix4.c +22 −33 Original line number Diff line number Diff line Loading @@ -52,6 +52,7 @@ struct pci_status { typedef struct PIIX4PMState { PCIDevice dev; IORange ioport; uint16_t pmsts; uint16_t pmen; uint16_t pmcntrl; Loading Loading @@ -128,10 +129,16 @@ static void pm_tmr_timer(void *opaque) pm_update_sci(s); } static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val) static void pm_ioport_write(IORange *ioport, uint64_t addr, unsigned width, uint64_t val) { PIIX4PMState *s = opaque; addr &= 0x3f; PIIX4PMState *s = container_of(ioport, PIIX4PMState, ioport); if (width != 2) { PIIX4_DPRINTF("PM write port=0x%04x width=%d val=0x%08x\n", (unsigned)addr, width, (unsigned)val); } switch(addr) { case 0x00: { Loading Loading @@ -184,12 +191,12 @@ static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val) PIIX4_DPRINTF("PM writew port=0x%04x val=0x%04x\n", addr, val); } static uint32_t pm_ioport_readw(void *opaque, uint32_t addr) static void pm_ioport_read(IORange *ioport, uint64_t addr, unsigned width, uint64_t *data) { PIIX4PMState *s = opaque; PIIX4PMState *s = container_of(ioport, PIIX4PMState, ioport); uint32_t val; addr &= 0x3f; switch(addr) { case 0x00: val = get_pmsts(s); Loading @@ -200,27 +207,6 @@ static uint32_t pm_ioport_readw(void *opaque, uint32_t addr) case 0x04: val = s->pmcntrl; break; default: val = 0; break; } PIIX4_DPRINTF("PM readw port=0x%04x val=0x%04x\n", addr, val); return val; } static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val) { // PIIX4PMState *s = opaque; PIIX4_DPRINTF("PM writel port=0x%04x val=0x%08x\n", addr & 0x3f, val); } static uint32_t pm_ioport_readl(void *opaque, uint32_t addr) { PIIX4PMState *s = opaque; uint32_t val; addr &= 0x3f; switch(addr) { case 0x08: val = get_pmtmr(s); break; Loading @@ -228,10 +214,15 @@ static uint32_t pm_ioport_readl(void *opaque, uint32_t addr) val = 0; break; } PIIX4_DPRINTF("PM readl port=0x%04x val=0x%08x\n", addr, val); return val; PIIX4_DPRINTF("PM readw port=0x%04x val=0x%04x\n", addr, val); *data = val; } static const IORangeOps pm_iorange_ops = { .read = pm_ioport_read, .write = pm_ioport_write, }; static void apm_ctrl_changed(uint32_t val, void *arg) { PIIX4PMState *s = arg; Loading Loading @@ -265,10 +256,8 @@ static void pm_io_space_update(PIIX4PMState *s) /* XXX: need to improve memory and ioport allocation */ PIIX4_DPRINTF("PM: mapping to 0x%x\n", pm_io_base); register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s); register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s); register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s); register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s); iorange_init(&s->ioport, &pm_iorange_ops, pm_io_base, 64); ioport_register(&s->ioport); } } Loading Loading
hw/acpi_piix4.c +22 −33 Original line number Diff line number Diff line Loading @@ -52,6 +52,7 @@ struct pci_status { typedef struct PIIX4PMState { PCIDevice dev; IORange ioport; uint16_t pmsts; uint16_t pmen; uint16_t pmcntrl; Loading Loading @@ -128,10 +129,16 @@ static void pm_tmr_timer(void *opaque) pm_update_sci(s); } static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val) static void pm_ioport_write(IORange *ioport, uint64_t addr, unsigned width, uint64_t val) { PIIX4PMState *s = opaque; addr &= 0x3f; PIIX4PMState *s = container_of(ioport, PIIX4PMState, ioport); if (width != 2) { PIIX4_DPRINTF("PM write port=0x%04x width=%d val=0x%08x\n", (unsigned)addr, width, (unsigned)val); } switch(addr) { case 0x00: { Loading Loading @@ -184,12 +191,12 @@ static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val) PIIX4_DPRINTF("PM writew port=0x%04x val=0x%04x\n", addr, val); } static uint32_t pm_ioport_readw(void *opaque, uint32_t addr) static void pm_ioport_read(IORange *ioport, uint64_t addr, unsigned width, uint64_t *data) { PIIX4PMState *s = opaque; PIIX4PMState *s = container_of(ioport, PIIX4PMState, ioport); uint32_t val; addr &= 0x3f; switch(addr) { case 0x00: val = get_pmsts(s); Loading @@ -200,27 +207,6 @@ static uint32_t pm_ioport_readw(void *opaque, uint32_t addr) case 0x04: val = s->pmcntrl; break; default: val = 0; break; } PIIX4_DPRINTF("PM readw port=0x%04x val=0x%04x\n", addr, val); return val; } static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val) { // PIIX4PMState *s = opaque; PIIX4_DPRINTF("PM writel port=0x%04x val=0x%08x\n", addr & 0x3f, val); } static uint32_t pm_ioport_readl(void *opaque, uint32_t addr) { PIIX4PMState *s = opaque; uint32_t val; addr &= 0x3f; switch(addr) { case 0x08: val = get_pmtmr(s); break; Loading @@ -228,10 +214,15 @@ static uint32_t pm_ioport_readl(void *opaque, uint32_t addr) val = 0; break; } PIIX4_DPRINTF("PM readl port=0x%04x val=0x%08x\n", addr, val); return val; PIIX4_DPRINTF("PM readw port=0x%04x val=0x%04x\n", addr, val); *data = val; } static const IORangeOps pm_iorange_ops = { .read = pm_ioport_read, .write = pm_ioport_write, }; static void apm_ctrl_changed(uint32_t val, void *arg) { PIIX4PMState *s = arg; Loading Loading @@ -265,10 +256,8 @@ static void pm_io_space_update(PIIX4PMState *s) /* XXX: need to improve memory and ioport allocation */ PIIX4_DPRINTF("PM: mapping to 0x%x\n", pm_io_base); register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s); register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s); register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s); register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s); iorange_init(&s->ioport, &pm_iorange_ops, pm_io_base, 64); ioport_register(&s->ioport); } } Loading