Commit 286d52eb authored by Aurelien Jarno's avatar Aurelien Jarno
Browse files

target-mips: don't flush extra TLB on permissions upgrade 



If the guest uses a TLBWI instruction for upgrading permissions, we
don't need to flush the extra TLBs. This improve boot time performance
by about 10%.

Signed-off-by: default avatarAurelien Jarno <aurelien@aurel32.net>
parent bc3e45e1

target-mips/op_helper.c

+23 −5
Original line number Diff line number Diff line
@@ -1819,14 +1819,32 @@ static void r4k_fill_tlb(CPUMIPSState *env, int idx) 


void r4k_helper_tlbwi(CPUMIPSState *env)

{

    r4k_tlb_t *tlb;

    int idx;

    target_ulong VPN;

    uint8_t ASID;

    bool G, V0, D0, V1, D1;



    idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;



    /* Discard cached TLB entries.  We could avoid doing this if the

       tlbwi is just upgrading access permissions on the current entry;

       that might be a further win.  */

    tlb = &env->tlb->mmu.r4k.tlb[idx];

    VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);

#if defined(TARGET_MIPS64)

    VPN &= env->SEGMask;

#endif

    ASID = env->CP0_EntryHi & 0xff;

    G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;

    V0 = (env->CP0_EntryLo0 & 2) != 0;

    D0 = (env->CP0_EntryLo0 & 4) != 0;

    V1 = (env->CP0_EntryLo1 & 2) != 0;

    D1 = (env->CP0_EntryLo1 & 4) != 0;



    /* Discard cached TLB entries, unless tlbwi is just upgrading access

       permissions on the current entry. */

    if (tlb->VPN != VPN || tlb->ASID != ASID || tlb->G != G ||

        (tlb->V0 && !V0) || (tlb->D0 && !D0) ||

        (tlb->V1 && !V1) || (tlb->D1 && !D1)) {

        r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);

    }



    r4k_invalidate_tlb(env, idx, 0);

    r4k_fill_tlb(env, idx);