Commit 27a4a30e authored by Yoshinori Sato's avatar Yoshinori Sato Committed by Philippe Mathieu-Daudé
Browse files

target/rx: CPU definitions 



Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Signed-off-by: default avatarYoshinori Sato <ysato@users.sourceforge.jp>
Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
[PMD: Use newer QOM style, split cpu-qom.h, restrict access to
 extable array, use rx_cpu_tlb_fill() extracted from patch of
 Yoshinori Sato 'Convert to CPUClass::tlb_fill', call cpu_reset
 after qemu_init_vcpu, make rx_crname a function]
Signed-off-by: default avatarPhilippe Mathieu-Daudé <philmd@redhat.com>
Acked-by: default avatarIgor Mammedov <imammedo@redhat.com>
Message-Id: <20200224141923.82118-7-ysato@users.sourceforge.jp>
Acked-by: default avatarRichard Henderson <richard.henderson@linaro.org>
[PMD: Use GByteArray in gdbstub (rebase commit a010bdbe),
 use device_class_set_parent_reset (rebase commit 781c67ca)]
Signed-off-by: default avatarPhilippe Mathieu-Daudé <f4bug@amsat.org>
parent 075d047e

gdb-xml/rx-core.xml

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<?xml version="1.0"?>

<!-- Copyright (C) 2019 Free Software Foundation, Inc.



     Copying and distribution of this file, with or without modification,

     are permitted in any medium without royalty provided the copyright

     notice and this notice are preserved.  -->



<!DOCTYPE feature SYSTEM "gdb-target.dtd">

<feature name="org.gnu.gdb.rx.core">

  <reg name="r0" bitsize="32" type="data_ptr"/>

  <reg name="r1" bitsize="32" type="uint32"/>

  <reg name="r2" bitsize="32" type="uint32"/>

  <reg name="r3" bitsize="32" type="uint32"/>

  <reg name="r4" bitsize="32" type="uint32"/>

  <reg name="r5" bitsize="32" type="uint32"/>

  <reg name="r6" bitsize="32" type="uint32"/>

  <reg name="r7" bitsize="32" type="uint32"/>

  <reg name="r8" bitsize="32" type="uint32"/>

  <reg name="r9" bitsize="32" type="uint32"/>

  <reg name="r10" bitsize="32" type="uint32"/>

  <reg name="r11" bitsize="32" type="uint32"/>

  <reg name="r12" bitsize="32" type="uint32"/>

  <reg name="r13" bitsize="32" type="uint32"/>

  <reg name="r14" bitsize="32" type="uint32"/>

  <reg name="r15" bitsize="32" type="uint32"/>



  <flags id="psw_flags" size="4">

    <field name="C" start="0" end="0"/>

    <field name="Z" start="1" end="1"/>

    <field name="S" start="2" end="2"/>

    <field name="O" start="3" end="3"/>

    <field name="I" start="16" end="16"/>

    <field name="U" start="17" end="17"/>

    <field name="PM" start="20" end="20"/>

    <field name="IPL" start="24" end="27"/>

  </flags>



  <flags id="fpsw_flags" size="4">

    <field name="RM" start="0" end="1"/>

    <field name="CV" start="2" end="2"/>

    <field name="CO" start="3" end="3"/>

    <field name="CZ" start="4" end="4"/>

    <field name="CU" start="5" end="5"/>

    <field name="CX" start="6" end="6"/>

    <field name="CE" start="7" end="7"/>

    <field name="DN" start="8" end="8"/>

    <field name="EV" start="10" end="10"/>

    <field name="EO" start="11" end="11"/>

    <field name="EZ" start="12" end="12"/>

    <field name="EU" start="13" end="13"/>

    <field name="EX" start="14" end="14"/>

    <field name="FV" start="26" end="26"/>

    <field name="FO" start="27" end="27"/>

    <field name="FZ" start="28" end="28"/>

    <field name="FU" start="29" end="29"/>

    <field name="FX" start="30" end="30"/>

    <field name="FS" start="31" end="31"/>

  </flags>



  <reg name="usp" bitsize="32" type="data_ptr"/>

  <reg name="isp" bitsize="32" type="data_ptr"/>

  <reg name="psw" bitsize="32" type="psw_flags"/>

  <reg name="pc" bitsize="32" type="code_ptr"/>

  <reg name="intb" bitsize="32" type="data_ptr"/>

  <reg name="bpsw" bitsize="32" type="psw_flags"/>

  <reg name="bpc" bitsize="32" type="code_ptr"/>

  <reg name="fintv" bitsize="32" type="code_ptr"/>

  <reg name="fpsw" bitsize="32" type="fpsw_flags"/>

  <reg name="acc" bitsize="64" type="uint64"/>

</feature>

target/rx/Makefile.objs

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obj-y += translate.o op_helper.o helper.o cpu.o gdbstub.o disas.o

obj-$(CONFIG_SOFTMMU) += monitor.o



DECODETREE = $(SRC_PATH)/scripts/decodetree.py

target/rx/cpu-param.h

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/*

 *  RX cpu parameters

 *

 *  Copyright (c) 2019 Yoshinori Sato

 *

 * This program is free software; you can redistribute it and/or modify it

 * under the terms and conditions of the GNU General Public License,

 * version 2 or later, as published by the Free Software Foundation.

 *

 * This program is distributed in the hope it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

 * more details.

 *

 * You should have received a copy of the GNU General Public License along with

 * this program.  If not, see <http://www.gnu.org/licenses/>.

 */



#ifndef RX_CPU_PARAM_H

#define RX_CPU_PARAM_H



#define TARGET_LONG_BITS 32

#define TARGET_PAGE_BITS 12



#define TARGET_PHYS_ADDR_SPACE_BITS 32

#define TARGET_VIRT_ADDR_SPACE_BITS 32



#define NB_MMU_MODES 1



#endif

target/rx/cpu-qom.h

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/*

 * RX CPU

 *

 * Copyright (c) 2019 Yoshinori Sato

 *

 * This program is free software; you can redistribute it and/or modify it

 * under the terms and conditions of the GNU General Public License,

 * version 2 or later, as published by the Free Software Foundation.

 *

 * This program is distributed in the hope it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

 * more details.

 *

 * You should have received a copy of the GNU General Public License along with

 * this program.  If not, see <http://www.gnu.org/licenses/>.

 */



#ifndef RX_CPU_QOM_H

#define RX_CPU_QOM_H



#include "hw/core/cpu.h"



#define TYPE_RX_CPU "rx-cpu"



#define TYPE_RX62N_CPU RX_CPU_TYPE_NAME("rx62n")



#define RXCPU_CLASS(klass) \

    OBJECT_CLASS_CHECK(RXCPUClass, (klass), TYPE_RX_CPU)

#define RXCPU(obj) \

    OBJECT_CHECK(RXCPU, (obj), TYPE_RX_CPU)

#define RXCPU_GET_CLASS(obj) \

    OBJECT_GET_CLASS(RXCPUClass, (obj), TYPE_RX_CPU)



/*

 * RXCPUClass:

 * @parent_realize: The parent class' realize handler.

 * @parent_reset: The parent class' reset handler.

 *

 * A RX CPU model.

 */

typedef struct RXCPUClass {

    /*< private >*/

    CPUClass parent_class;

    /*< public >*/



    DeviceRealize parent_realize;

    DeviceReset parent_reset;

} RXCPUClass;



#define CPUArchState struct CPURXState



#endif

target/rx/cpu.c

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/*

 * QEMU RX CPU

 *

 * Copyright (c) 2019 Yoshinori Sato

 *

 * This program is free software; you can redistribute it and/or modify it

 * under the terms and conditions of the GNU General Public License,

 * version 2 or later, as published by the Free Software Foundation.

 *

 * This program is distributed in the hope it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

 * more details.

 *

 * You should have received a copy of the GNU General Public License along with

 * this program.  If not, see <http://www.gnu.org/licenses/>.

 */



#include "qemu/osdep.h"

#include "qemu/qemu-print.h"

#include "qapi/error.h"

#include "cpu.h"

#include "qemu-common.h"

#include "migration/vmstate.h"

#include "exec/exec-all.h"

#include "hw/loader.h"

#include "fpu/softfloat.h"



static void rx_cpu_set_pc(CPUState *cs, vaddr value)

{

    RXCPU *cpu = RXCPU(cs);



    cpu->env.pc = value;

}



static void rx_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)

{

    RXCPU *cpu = RXCPU(cs);



    cpu->env.pc = tb->pc;

}



static bool rx_cpu_has_work(CPUState *cs)

{

    return cs->interrupt_request &

        (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR);

}



static void rx_cpu_reset(DeviceState *dev)

{

    RXCPU *cpu = RXCPU(dev);

    RXCPUClass *rcc = RXCPU_GET_CLASS(cpu);

    CPURXState *env = &cpu->env;

    uint32_t *resetvec;



    rcc->parent_reset(dev);



    memset(env, 0, offsetof(CPURXState, end_reset_fields));



    resetvec = rom_ptr(0xfffffffc, 4);

    if (resetvec) {

        /* In the case of kernel, it is ignored because it is not set. */

        env->pc = ldl_p(resetvec);

    }

    rx_cpu_unpack_psw(env, 0, 1);

    env->regs[0] = env->isp = env->usp = 0;

    env->fpsw = 0;

    set_flush_to_zero(1, &env->fp_status);

    set_flush_inputs_to_zero(1, &env->fp_status);

}



static void rx_cpu_list_entry(gpointer data, gpointer user_data)

{

    ObjectClass *oc = data;



    qemu_printf("  %s\n", object_class_get_name(oc));

}



void rx_cpu_list(void)

{

    GSList *list;

    list = object_class_get_list_sorted(TYPE_RX_CPU, false);

    qemu_printf("Available CPUs:\n");

    g_slist_foreach(list, rx_cpu_list_entry, NULL);

    g_slist_free(list);

}



static ObjectClass *rx_cpu_class_by_name(const char *cpu_model)

{

    ObjectClass *oc;

    char *typename;



    oc = object_class_by_name(cpu_model);

    if (oc != NULL && object_class_dynamic_cast(oc, TYPE_RX_CPU) != NULL &&

        !object_class_is_abstract(oc)) {

        return oc;

    }

    typename = g_strdup_printf(RX_CPU_TYPE_NAME("%s"), cpu_model);

    oc = object_class_by_name(typename);

    g_free(typename);

    if (oc != NULL && object_class_is_abstract(oc)) {

        oc = NULL;

    }



    return oc;

}



static void rx_cpu_realize(DeviceState *dev, Error **errp)

{

    CPUState *cs = CPU(dev);

    RXCPUClass *rcc = RXCPU_GET_CLASS(dev);

    Error *local_err = NULL;



    cpu_exec_realizefn(cs, &local_err);

    if (local_err != NULL) {

        error_propagate(errp, local_err);

        return;

    }



    qemu_init_vcpu(cs);

    cpu_reset(cs);



    rcc->parent_realize(dev, errp);

}



static void rx_cpu_set_irq(void *opaque, int no, int request)

{

    RXCPU *cpu = opaque;

    CPUState *cs = CPU(cpu);

    int irq = request & 0xff;



    static const int mask[] = {

        [RX_CPU_IRQ] = CPU_INTERRUPT_HARD,

        [RX_CPU_FIR] = CPU_INTERRUPT_FIR,

    };

    if (irq) {

        cpu->env.req_irq = irq;

        cpu->env.req_ipl = (request >> 8) & 0x0f;

        cpu_interrupt(cs, mask[no]);

    } else {

        cpu_reset_interrupt(cs, mask[no]);

    }

}



static void rx_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)

{

    info->mach = bfd_mach_rx;

    info->print_insn = print_insn_rx;

}



static bool rx_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,

                            MMUAccessType access_type, int mmu_idx,

                            bool probe, uintptr_t retaddr)

{

    uint32_t address, physical, prot;



    /* Linear mapping */

    address = physical = addr & TARGET_PAGE_MASK;

    prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;

    tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE);

    return true;

}



static void rx_cpu_init(Object *obj)

{

    CPUState *cs = CPU(obj);

    RXCPU *cpu = RXCPU(obj);

    CPURXState *env = &cpu->env;



    cpu_set_cpustate_pointers(cpu);

    cs->env_ptr = env;

    qdev_init_gpio_in(DEVICE(cpu), rx_cpu_set_irq, 2);

}



static void rx_cpu_class_init(ObjectClass *klass, void *data)

{

    DeviceClass *dc = DEVICE_CLASS(klass);

    CPUClass *cc = CPU_CLASS(klass);

    RXCPUClass *rcc = RXCPU_CLASS(klass);



    device_class_set_parent_realize(dc, rx_cpu_realize,

                                    &rcc->parent_realize);

    device_class_set_parent_reset(dc, rx_cpu_reset,

                                  &rcc->parent_reset);



    cc->class_by_name = rx_cpu_class_by_name;

    cc->has_work = rx_cpu_has_work;

    cc->do_interrupt = rx_cpu_do_interrupt;

    cc->cpu_exec_interrupt = rx_cpu_exec_interrupt;

    cc->dump_state = rx_cpu_dump_state;

    cc->set_pc = rx_cpu_set_pc;

    cc->synchronize_from_tb = rx_cpu_synchronize_from_tb;

    cc->gdb_read_register = rx_cpu_gdb_read_register;

    cc->gdb_write_register = rx_cpu_gdb_write_register;

    cc->get_phys_page_debug = rx_cpu_get_phys_page_debug;

    cc->disas_set_info = rx_cpu_disas_set_info;

    cc->tcg_initialize = rx_translate_init;

    cc->tlb_fill = rx_cpu_tlb_fill;



    cc->gdb_num_core_regs = 26;

    cc->gdb_core_xml_file = "rx-core.xml";

}



static const TypeInfo rx_cpu_info = {

    .name = TYPE_RX_CPU,

    .parent = TYPE_CPU,

    .instance_size = sizeof(RXCPU),

    .instance_init = rx_cpu_init,

    .abstract = true,

    .class_size = sizeof(RXCPUClass),

    .class_init = rx_cpu_class_init,

};



static const TypeInfo rx62n_rx_cpu_info = {

    .name = TYPE_RX62N_CPU,

    .parent = TYPE_RX_CPU,

};



static void rx_cpu_register_types(void)

{

    type_register_static(&rx_cpu_info);

    type_register_static(&rx62n_rx_cpu_info);

}



type_init(rx_cpu_register_types)