Unverified Commit 25fa194b authored by Michael Clark's avatar Michael Clark
Browse files

RISC-V Build Infrastructure 



This adds RISC-V into the build system enabling the following targets:

- riscv32-softmmu
- riscv64-softmmu
- riscv32-linux-user
- riscv64-linux-user

This adds defaults configs for RISC-V, enables the build for the RISC-V
CPU core, hardware, and Linux User Emulation. The 'qemu-binfmt-conf.sh'
script is updated to add the RISC-V ELF magic.

Expected checkpatch errors for consistency reasons:

ERROR: line over 90 characters
FILE: scripts/qemu-binfmt-conf.sh

Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Signed-off-by: default avatarSagar Karandikar <sagark@eecs.berkeley.edu>
Signed-off-by: default avatarMichael Clark <mjc@sifive.com>
parent a7240d1e

arch_init.c

+2 −0
Original line number Diff line number Diff line
@@ -71,6 +71,8 @@ int graphic_depth = 32; 
#define QEMU_ARCH QEMU_ARCH_OPENRISC

#elif defined(TARGET_PPC)

#define QEMU_ARCH QEMU_ARCH_PPC

#elif defined(TARGET_RISCV)

#define QEMU_ARCH QEMU_ARCH_RISCV

#elif defined(TARGET_S390X)

#define QEMU_ARCH QEMU_ARCH_S390X

#elif defined(TARGET_SH4)

configure

+13 −0
Original line number Diff line number Diff line
@@ -6797,6 +6797,16 @@ case "$target_name" in 
    echo "TARGET_ABI32=y" >> $config_target_mak

    gdb_xml_files="power64-core.xml power-fpu.xml power-altivec.xml power-spe.xml power-vsx.xml"

  ;;

  riscv32)

    TARGET_BASE_ARCH=riscv

    TARGET_ABI_DIR=riscv

    mttcg=yes

  ;;

  riscv64)

    TARGET_BASE_ARCH=riscv

    TARGET_ABI_DIR=riscv

    mttcg=yes

  ;;

  sh4|sh4eb)

    TARGET_ARCH=sh4

    bflt="yes"
@@ -6966,6 +6976,9 @@ for i in $ARCH $TARGET_BASE_ARCH ; do 
  ppc*)

    disas_config "PPC"

  ;;

  riscv)

    disas_config "RISCV"

  ;;

  s390*)

    disas_config "S390"

  ;;

cpus.c

+6 −0
Original line number Diff line number Diff line
@@ -2081,6 +2081,9 @@ CpuInfoList *qmp_query_cpus(Error **errp) 
#elif defined(TARGET_SPARC)

        SPARCCPU *sparc_cpu = SPARC_CPU(cpu);

        CPUSPARCState *env = &sparc_cpu->env;

#elif defined(TARGET_RISCV)

        RISCVCPU *riscv_cpu = RISCV_CPU(cpu);

        CPURISCVState *env = &riscv_cpu->env;

#elif defined(TARGET_MIPS)

        MIPSCPU *mips_cpu = MIPS_CPU(cpu);

        CPUMIPSState *env = &mips_cpu->env;
@@ -2120,6 +2123,9 @@ CpuInfoList *qmp_query_cpus(Error **errp) 
#elif defined(TARGET_S390X)

        info->value->arch = CPU_INFO_ARCH_S390;

        info->value->u.s390.cpu_state = env->cpu_state;

#elif defined(TARGET_RISCV)

        info->value->arch = CPU_INFO_ARCH_RISCV;

        info->value->u.riscv.pc = env->pc;

#else

        info->value->arch = CPU_INFO_ARCH_OTHER;

#endif

default-configs/riscv32-linux-user.mak

0 → 100644
+1 −0
Original line number Diff line number Diff line 
# Default configuration for riscv-linux-user

default-configs/riscv32-softmmu.mak

0 → 100644
+4 −0
Original line number Diff line number Diff line 
# Default configuration for riscv-softmmu



CONFIG_SERIAL=y

CONFIG_VIRTIO=y