Loading target-ppc/translate.c +11 −18 Original line number Diff line number Diff line Loading @@ -756,27 +756,20 @@ static void gen_cmpli(DisasContext *ctx) /* isel (PowerPC 2.03 specification) */ static void gen_isel(DisasContext *ctx) { TCGLabel *l1, *l2; uint32_t bi = rC(ctx->opcode); uint32_t mask; TCGv_i32 t0; uint32_t mask = 0x08 >> (bi & 0x03); TCGv t0 = tcg_temp_new(); TCGv zr; l1 = gen_new_label(); l2 = gen_new_label(); tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); tcg_gen_andi_tl(t0, t0, mask); mask = 0x08 >> (bi & 0x03); t0 = tcg_temp_new_i32(); tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask); tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1); if (rA(ctx->opcode) == 0) tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); else tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); tcg_gen_br(l2); gen_set_label(l1); tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); gen_set_label(l2); tcg_temp_free_i32(t0); zr = tcg_const_tl(0); tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, cpu_gpr[rB(ctx->opcode)]); tcg_temp_free(zr); tcg_temp_free(t0); } /* cmpb: PowerPC 2.05 specification */ Loading Loading
target-ppc/translate.c +11 −18 Original line number Diff line number Diff line Loading @@ -756,27 +756,20 @@ static void gen_cmpli(DisasContext *ctx) /* isel (PowerPC 2.03 specification) */ static void gen_isel(DisasContext *ctx) { TCGLabel *l1, *l2; uint32_t bi = rC(ctx->opcode); uint32_t mask; TCGv_i32 t0; uint32_t mask = 0x08 >> (bi & 0x03); TCGv t0 = tcg_temp_new(); TCGv zr; l1 = gen_new_label(); l2 = gen_new_label(); tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); tcg_gen_andi_tl(t0, t0, mask); mask = 0x08 >> (bi & 0x03); t0 = tcg_temp_new_i32(); tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask); tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1); if (rA(ctx->opcode) == 0) tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); else tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); tcg_gen_br(l2); gen_set_label(l1); tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); gen_set_label(l2); tcg_temp_free_i32(t0); zr = tcg_const_tl(0); tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, cpu_gpr[rB(ctx->opcode)]); tcg_temp_free(zr); tcg_temp_free(t0); } /* cmpb: PowerPC 2.05 specification */ Loading