Commit 24c32852 authored by Richard Henderson's avatar Richard Henderson
Browse files

target/openrisc: Tidy ppc/npc implementation 



The NPC SPR is really only supposed to be used for FPGA debugging.
It contains the same contents as PC, unless one plays games.  Follow
the or1ksim implementation in flushing delayed branch state when it
is changed.

The PPC SPR need not be updated every instruction, merely when we
exit the TB or attempt to read its contents.

Signed-off-by: default avatarRichard Henderson <rth@twiddle.net>
parent a8000cb4

target/openrisc/cpu.h

+1 −1
Original line number Diff line number Diff line
@@ -58,6 +58,7 @@ typedef struct OpenRISCCPUClass { 
} OpenRISCCPUClass;



#define NB_MMU_MODES    3

#define TARGET_INSN_START_EXTRA_WORDS 1



enum {

    MMU_NOMMU_IDX = 0,
@@ -273,7 +274,6 @@ typedef struct CPUOpenRISCTLBContext { 
typedef struct CPUOpenRISCState {

    target_ulong gpr[32];     /* General registers */

    target_ulong pc;          /* Program counter */

    target_ulong npc;         /* Next PC */

    target_ulong ppc;         /* Prev PC */

    target_ulong jmp_pc;      /* Jump PC */

target/openrisc/gdbstub.c

+9 −4
Original line number Diff line number Diff line
@@ -34,8 +34,8 @@ int openrisc_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) 
        case 32:    /* PPC */

            return gdb_get_reg32(mem_buf, env->ppc);



        case 33:    /* NPC */

            return gdb_get_reg32(mem_buf, env->npc);

        case 33:    /* NPC (equals PC) */

            return gdb_get_reg32(mem_buf, env->pc);



        case 34:    /* SR */

            return gdb_get_reg32(mem_buf, cpu_get_sr(env));
@@ -68,8 +68,13 @@ int openrisc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) 
            env->ppc = tmp;

            break;



        case 33: /* NPC */

            env->npc = tmp;

        case 33: /* NPC (equals PC) */

            /* If setting PC to something different,

               also clear delayed branch status.  */

            if (env->pc != tmp) {

                env->pc = tmp;

                env->flags = 0;

            }

            break;



        case 34: /* SR */

target/openrisc/interrupt_helper.c

+0 −1
Original line number Diff line number Diff line
@@ -32,7 +32,6 @@ void HELPER(rfe)(CPUOpenRISCState *env) 
                         (cpu->env.esr & (SR_SM | SR_IME | SR_DME));

#endif

    cpu->env.pc = cpu->env.epcr;

    cpu->env.npc = cpu->env.epcr;

    cpu_set_sr(&cpu->env, cpu->env.esr);

    cpu->env.lock_addr = -1;

target/openrisc/machine.c

+2 −3
Original line number Diff line number Diff line
@@ -47,12 +47,11 @@ static const VMStateInfo vmstate_sr = { 


static const VMStateDescription vmstate_env = {

    .name = "env",

    .version_id = 3,

    .minimum_version_id = 3,

    .version_id = 4,

    .minimum_version_id = 4,

    .fields = (VMStateField[]) {

        VMSTATE_UINTTL_ARRAY(gpr, CPUOpenRISCState, 32),

        VMSTATE_UINTTL(pc, CPUOpenRISCState),

        VMSTATE_UINTTL(npc, CPUOpenRISCState),

        VMSTATE_UINTTL(ppc, CPUOpenRISCState),

        VMSTATE_UINTTL(jmp_pc, CPUOpenRISCState),

        VMSTATE_UINTTL(lock_addr, CPUOpenRISCState),

target/openrisc/sys_helper.c

+16 −28
Original line number Diff line number Diff line
@@ -29,11 +29,10 @@ void HELPER(mtspr)(CPUOpenRISCState *env, 
                   target_ulong ra, target_ulong rb, target_ulong offset)

{

#ifndef CONFIG_USER_ONLY

    int spr = (ra | offset);

    int idx;



    OpenRISCCPU *cpu = openrisc_env_get_cpu(env);

    CPUState *cs = CPU(cpu);

    int spr = (ra | offset);

    int idx;



    switch (spr) {

    case TO_SPR(0, 0): /* VR */
@@ -41,7 +40,14 @@ void HELPER(mtspr)(CPUOpenRISCState *env, 
        break;



    case TO_SPR(0, 16): /* NPC */

        env->npc = rb;

        cpu_restore_state(cs, GETPC());

        /* ??? Mirror or1ksim in not trashing delayed branch state

           when "jumping" to the current instruction.  */

        if (env->pc != rb) {

            env->pc = rb;

            env->flags = 0;

            cpu_loop_exit(cs);

        }

        break;



    case TO_SPR(0, 17): /* SR */
@@ -170,7 +176,6 @@ void HELPER(mtspr)(CPUOpenRISCState *env, 
        cpu_openrisc_timer_update(cpu);

        break;

    default:



        break;

    }

#endif
@@ -180,11 +185,11 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, 
                           target_ulong rd, target_ulong ra, uint32_t offset)

{

#ifndef CONFIG_USER_ONLY

    OpenRISCCPU *cpu = openrisc_env_get_cpu(env);

    CPUState *cs = CPU(cpu);

    int spr = (ra | offset);

    int idx;



    OpenRISCCPU *cpu = openrisc_env_get_cpu(env);



    switch (spr) {

    case TO_SPR(0, 0): /* VR */

        return env->vr & SPR_VR;
@@ -201,13 +206,15 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, 
    case TO_SPR(0, 4): /* IMMUCFGR */

        return env->immucfgr;



    case TO_SPR(0, 16): /* NPC */

        return env->npc;

    case TO_SPR(0, 16): /* NPC (equals PC) */

        cpu_restore_state(cs, GETPC());

        return env->pc;



    case TO_SPR(0, 17): /* SR */

        return cpu_get_sr(env);



    case TO_SPR(0, 18): /* PPC */

        cpu_restore_state(cs, GETPC());

        return env->ppc;



    case TO_SPR(0, 32): /* EPCR */
@@ -276,25 +283,6 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, 
    }

#endif



/*If we later need to add tracepoints (or debug printfs) for the return

value, it may be useful to structure the code like this:



target_ulong ret = 0;



switch() {

case x:

 ret = y;

 break;

case z:

 ret = 42;

 break;

...

}



later something like trace_spr_read(ret);



return ret;*/



    /* for rd is passed in, if rd unchanged, just keep it back.  */

    return rd;

}