Commit 2409d564 authored by Richard Henderson's avatar Richard Henderson Committed by Peter Maydell
Browse files

target/arm: Simplify UMAAL 



Since all of the inputs and outputs are i32, dispense with
the intermediate promotion to i64 and use tcg_gen_mulu2_i32
and tcg_gen_add2_i32.

Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Message-id: 20190904193059.26202-8-richard.henderson@linaro.org
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent bd92fe35

target/arm/translate.c

+12 −22
Original line number Diff line number Diff line
@@ -7346,21 +7346,6 @@ static void gen_storeq_reg(DisasContext *s, int rlow, int rhigh, TCGv_i64 val) 
    store_reg(s, rhigh, tmp);

}



/* load a 32-bit value from a register and perform a 64-bit accumulate.  */

static void gen_addq_lo(DisasContext *s, TCGv_i64 val, int rlow)

{

    TCGv_i64 tmp;

    TCGv_i32 tmp2;



    /* Load value and extend to 64 bits.  */

    tmp = tcg_temp_new_i64();

    tmp2 = load_reg(s, rlow);

    tcg_gen_extu_i32_i64(tmp, tmp2);

    tcg_temp_free_i32(tmp2);

    tcg_gen_add_i64(val, val, tmp);

    tcg_temp_free_i64(tmp);

}



/* load and add a 64-bit value from a register pair.  */

static void gen_addq(DisasContext *s, TCGv_i64 val, int rlow, int rhigh)

{
@@ -8119,8 +8104,7 @@ static bool trans_SMLAL(DisasContext *s, arg_SMLAL *a) 


static bool trans_UMAAL(DisasContext *s, arg_UMAAL *a)

{

    TCGv_i32 t0, t1;

    TCGv_i64 t64;

    TCGv_i32 t0, t1, t2, zero;



    if (s->thumb

        ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)
@@ -8130,11 +8114,17 @@ static bool trans_UMAAL(DisasContext *s, arg_UMAAL *a) 


    t0 = load_reg(s, a->rm);

    t1 = load_reg(s, a->rn);

    t64 = gen_mulu_i64_i32(t0, t1);

    gen_addq_lo(s, t64, a->ra);

    gen_addq_lo(s, t64, a->rd);

    gen_storeq_reg(s, a->ra, a->rd, t64);

    tcg_temp_free_i64(t64);

    tcg_gen_mulu2_i32(t0, t1, t0, t1);

    zero = tcg_const_i32(0);

    t2 = load_reg(s, a->ra);

    tcg_gen_add2_i32(t0, t1, t0, t1, t2, zero);

    tcg_temp_free_i32(t2);

    t2 = load_reg(s, a->rd);

    tcg_gen_add2_i32(t0, t1, t0, t1, t2, zero);

    tcg_temp_free_i32(t2);

    tcg_temp_free_i32(zero);

    store_reg(s, a->ra, t0);

    store_reg(s, a->rd, t1);

    return true;

}