Loading hw/sun4u.c +16 −13 Original line number Diff line number Diff line Loading @@ -309,21 +309,24 @@ static void cpu_set_ivec_irq(void *opaque, int irq, int level) CPUSPARCState *env = opaque; if (level) { if (!(env->ivec_status & 0x20)) { CPUIRQ_DPRINTF("Raise IVEC IRQ %d\n", irq); env->halted = 0; env->interrupt_index = TT_IVEC; env->pil_in |= 1 << 5; env->ivec_status |= 0x20; env->ivec_data[0] = (0x1f << 6) | irq; env->ivec_data[1] = 0; env->ivec_data[2] = 0; cpu_interrupt(env, CPU_INTERRUPT_HARD); } } else { if (env->ivec_status & 0x20) { CPUIRQ_DPRINTF("Lower IVEC IRQ %d\n", irq); env->pil_in &= ~(1 << 5); env->ivec_status &= ~0x20; cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); } } } typedef struct ResetData { CPUSPARCState *env; Loading Loading
hw/sun4u.c +16 −13 Original line number Diff line number Diff line Loading @@ -309,21 +309,24 @@ static void cpu_set_ivec_irq(void *opaque, int irq, int level) CPUSPARCState *env = opaque; if (level) { if (!(env->ivec_status & 0x20)) { CPUIRQ_DPRINTF("Raise IVEC IRQ %d\n", irq); env->halted = 0; env->interrupt_index = TT_IVEC; env->pil_in |= 1 << 5; env->ivec_status |= 0x20; env->ivec_data[0] = (0x1f << 6) | irq; env->ivec_data[1] = 0; env->ivec_data[2] = 0; cpu_interrupt(env, CPU_INTERRUPT_HARD); } } else { if (env->ivec_status & 0x20) { CPUIRQ_DPRINTF("Lower IVEC IRQ %d\n", irq); env->pil_in &= ~(1 << 5); env->ivec_status &= ~0x20; cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); } } } typedef struct ResetData { CPUSPARCState *env; Loading