Commit 23463e0e authored Nov 06, 2018 by Peter Maydell

target/arm: Fix ATS1Hx instructions



ATS1HR and ATS1HW (which allow AArch32 EL2 to do address translations
on the EL2 translation regime) were implemented in commit 14db7fe0.
However, we got them wrong: these should do stage 1 address translations
as defined for NS-EL2, which is ARMMMUIdx_S1E2. We were incorrectly
making them perform stage 2 translations.

A few years later in commit 1313e2d7 we forgot entirely that
we'd implemented ATS1Hx, and added a comment that ATS1Hx were
"not supported yet". Remove the comment; there is no extra code
needed to handle these operations in do_ats_write(), because
arm_s1_regime_using_lpae_format() returns true for ARMMMUIdx_S1E2,
which forces 64-bit PAR format.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20181016093703.10637-3-peter.maydell@linaro.org
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

parent 0f7b791b

target/arm/helper.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -2319,7 +2319,7 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
		*
		* (Note that HCR.DC makes HCR.VM behave as if it is 1.)
		*
		* ATS1Hx always uses the 64bit format (not supported yet).
		* ATS1Hx always uses the 64bit format.
		*/
		format64 = arm_s1_regime_using_lpae_format(env, mmu_idx);

		@@ -2444,7 +2444,7 @@ static void ats1h_write(CPUARMState env, const ARMCPRegInfo ri,
		MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD;
		uint64_t par64;

		par64 = do_ats_write(env, value, access_type, ARMMMUIdx_S2NS);
		par64 = do_ats_write(env, value, access_type, ARMMMUIdx_S1E2);

		A32_BANKED_CURRENT_REG_SET(env, par, par64);
		}