Commit 22c5f446 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190211' into staging 



Fix dynamic tlb resize
Fix x86 host vector saturation
Diagnose missing tcg labels

# gpg: Signature made Mon 11 Feb 2019 16:57:52 GMT
# gpg:                using RSA key 64DF38E8AF7E215F
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A  05C0 64DF 38E8 AF7E 215F

* remotes/rth/tags/pull-tcg-20190211:
  cputlb: update TLB entry/index after tlb_fill
  exec-all: document that tlb_fill can trigger a TLB resize
  tcg/i386: fix unsigned vector saturating arithmetic
  tcg: Diagnose referenced labels that have not been emitted

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents a044e3de 6d967cb8

accel/tcg/cputlb.c

+4 −0
Original line number Diff line number Diff line
@@ -1045,6 +1045,8 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env, target_ulong addr) 
    if (unlikely(!tlb_hit(entry->addr_code, addr))) {

        if (!VICTIM_TLB_HIT(addr_code, addr)) {

            tlb_fill(ENV_GET_CPU(env), addr, 0, MMU_INST_FETCH, mmu_idx, 0);

            index = tlb_index(env, mmu_idx, addr);

            entry = tlb_entry(env, mmu_idx, addr);

        }

        assert(tlb_hit(entry->addr_code, addr));

    }
@@ -1125,6 +1127,8 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, 
        if (!VICTIM_TLB_HIT(addr_write, addr)) {

            tlb_fill(ENV_GET_CPU(env), addr, 1 << s_bits, MMU_DATA_STORE,

                     mmu_idx, retaddr);

            index = tlb_index(env, mmu_idx, addr);

            tlbe = tlb_entry(env, mmu_idx, addr);

        }

        tlb_addr = tlb_addr_write(tlbe) & ~TLB_INVALID_MASK;

    }

accel/tcg/softmmu_template.h

+8 −0
Original line number Diff line number Diff line
@@ -129,6 +129,8 @@ WORD_TYPE helper_le_ld_name(CPUArchState *env, target_ulong addr, 
        if (!VICTIM_TLB_HIT(ADDR_READ, addr)) {

            tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, READ_ACCESS_TYPE,

                     mmu_idx, retaddr);

            index = tlb_index(env, mmu_idx, addr);

            entry = tlb_entry(env, mmu_idx, addr);

        }

        tlb_addr = entry->ADDR_READ;

    }
@@ -198,6 +200,8 @@ WORD_TYPE helper_be_ld_name(CPUArchState *env, target_ulong addr, 
        if (!VICTIM_TLB_HIT(ADDR_READ, addr)) {

            tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, READ_ACCESS_TYPE,

                     mmu_idx, retaddr);

            index = tlb_index(env, mmu_idx, addr);

            entry = tlb_entry(env, mmu_idx, addr);

        }

        tlb_addr = entry->ADDR_READ;

    }
@@ -294,6 +298,8 @@ void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val, 
        if (!VICTIM_TLB_HIT(addr_write, addr)) {

            tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, MMU_DATA_STORE,

                     mmu_idx, retaddr);

            index = tlb_index(env, mmu_idx, addr);

            entry = tlb_entry(env, mmu_idx, addr);

        }

        tlb_addr = tlb_addr_write(entry) & ~TLB_INVALID_MASK;

    }
@@ -372,6 +378,8 @@ void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val, 
        if (!VICTIM_TLB_HIT(addr_write, addr)) {

            tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, MMU_DATA_STORE,

                     mmu_idx, retaddr);

            index = tlb_index(env, mmu_idx, addr);

            entry = tlb_entry(env, mmu_idx, addr);

        }

        tlb_addr = tlb_addr_write(entry) & ~TLB_INVALID_MASK;

    }

include/exec/exec-all.h

+5 −0
Original line number Diff line number Diff line
@@ -475,6 +475,11 @@ static inline void assert_no_pages_locked(void) 
struct MemoryRegionSection *iotlb_to_section(CPUState *cpu,

                                             hwaddr index, MemTxAttrs attrs);



/*

 * Note: tlb_fill() can trigger a resize of the TLB. This means that all of the

 * caller's prior references to the TLB table (e.g. CPUTLBEntry pointers) must

 * be discarded and looked up again (e.g. via tlb_entry()).

 */

void tlb_fill(CPUState *cpu, target_ulong addr, int size,

              MMUAccessType access_type, int mmu_idx, uintptr_t retaddr);

tcg/i386/tcg-target.inc.c

+2 −2
Original line number Diff line number Diff line
@@ -2615,7 +2615,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, 
        OPC_PADDSB, OPC_PADDSW, OPC_UD2, OPC_UD2

    };

    static int const usadd_insn[4] = {

        OPC_PADDSB, OPC_PADDSW, OPC_UD2, OPC_UD2

        OPC_PADDUB, OPC_PADDUW, OPC_UD2, OPC_UD2

    };

    static int const sub_insn[4] = {

        OPC_PSUBB, OPC_PSUBW, OPC_PSUBD, OPC_PSUBQ
@@ -2624,7 +2624,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, 
        OPC_PSUBSB, OPC_PSUBSW, OPC_UD2, OPC_UD2

    };

    static int const ussub_insn[4] = {

        OPC_PSUBSB, OPC_PSUBSW, OPC_UD2, OPC_UD2

        OPC_PSUBUB, OPC_PSUBUW, OPC_UD2, OPC_UD2

    };

    static int const mul_insn[4] = {

        OPC_UD2, OPC_PMULLW, OPC_PMULLD, OPC_UD2

tcg/tcg-op.h

+1 −0
Original line number Diff line number Diff line
@@ -255,6 +255,7 @@ static inline void tcg_gen_op6ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, 


static inline void gen_set_label(TCGLabel *l)

{

    l->present = 1;

    tcg_gen_op1(INDEX_op_set_label, label_arg(l));

}