Commit 226cd207 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/philmd-gitlab/tags/target_renesas_rx-20200320' into staging 

Introduce the architectural part of the Renesas RX
architecture emulation, developed by Yoshinori Sato.

CI jobs results:
  https://gitlab.com/philmd/qemu/pipelines/127886344
  https://travis-ci.org/github/philmd/qemu/builds/664579420



# gpg: Signature made Fri 20 Mar 2020 10:27:32 GMT
# gpg:                using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD  6BB2 E3E3 2C2C DEAD C0DE

* remotes/philmd-gitlab/tags/target_renesas_rx-20200320:
  Add rx-softmmu
  target/rx: Dump bytes for each insn during disassembly
  target/rx: Collect all bytes during disassembly
  target/rx: Emit all disassembly in one prt()
  target/rx: Use prt_ldmi for XCHG_mr disassembly
  target/rx: Replace operand with prt_ldmi in disassembler
  target/rx: Disassemble rx_index_addr into a string
  target/rx: RX disassembler
  target/rx: CPU definitions
  target/rx: TCG helpers
  target/rx: TCG translation
  MAINTAINERS: Add entry for the Renesas RX architecture
  hw/registerfields.h: Add 8bit and 16bit register macros

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents f3949284 c8c35e5f

MAINTAINERS

+5 −0
Original line number Diff line number Diff line
@@ -277,6 +277,11 @@ F: include/hw/riscv/ 
F: linux-user/host/riscv32/

F: linux-user/host/riscv64/



RENESAS RX CPUs

M: Yoshinori Sato <ysato@users.sourceforge.jp>

S: Maintained

F: target/rx/



S390 TCG CPUs

M: Richard Henderson <rth@twiddle.net>

M: David Hildenbrand <david@redhat.com>

arch_init.c

+2 −0
Original line number Diff line number Diff line
@@ -77,6 +77,8 @@ int graphic_depth = 32; 
#define QEMU_ARCH QEMU_ARCH_PPC

#elif defined(TARGET_RISCV)

#define QEMU_ARCH QEMU_ARCH_RISCV

#elif defined(TARGET_RX)

#define QEMU_ARCH QEMU_ARCH_RX

#elif defined(TARGET_S390X)

#define QEMU_ARCH QEMU_ARCH_S390X

#elif defined(TARGET_SH4)

configure

+10 −1
Original line number Diff line number Diff line
@@ -4227,7 +4227,7 @@ fi 
fdt_required=no

for target in $target_list; do

  case $target in

    aarch64*-softmmu|arm*-softmmu|ppc*-softmmu|microblaze*-softmmu|mips64el-softmmu|riscv*-softmmu)

    aarch64*-softmmu|arm*-softmmu|ppc*-softmmu|microblaze*-softmmu|mips64el-softmmu|riscv*-softmmu|rx-softmmu)

      fdt_required=yes

    ;;

  esac
@@ -7912,6 +7912,12 @@ case "$target_name" in 
    mttcg=yes

    gdb_xml_files="riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-64bit-csr.xml riscv-64bit-virtual.xml"

  ;;

  rx)

    TARGET_ARCH=rx

    bflt="yes"

    target_compiler=$cross_cc_rx

    gdb_xml_files="rx-core.xml"

  ;;

  sh4|sh4eb)

    TARGET_ARCH=sh4

    bflt="yes"
@@ -8093,6 +8099,9 @@ for i in $ARCH $TARGET_BASE_ARCH ; do 
  riscv*)

    disas_config "RISCV"

  ;;

  rx)

    disas_config "RX"

  ;;

  s390*)

    disas_config "S390"

  ;;

default-configs/rx-softmmu.mak

0 → 100644
+2 −0
Original line number Diff line number Diff line 
# Default configuration for rx-softmmu

gdb-xml/rx-core.xml

0 → 100644
+70 −0
Original line number Diff line number Diff line 
<?xml version="1.0"?>

<!-- Copyright (C) 2019 Free Software Foundation, Inc.



     Copying and distribution of this file, with or without modification,

     are permitted in any medium without royalty provided the copyright

     notice and this notice are preserved.  -->



<!DOCTYPE feature SYSTEM "gdb-target.dtd">

<feature name="org.gnu.gdb.rx.core">

  <reg name="r0" bitsize="32" type="data_ptr"/>

  <reg name="r1" bitsize="32" type="uint32"/>

  <reg name="r2" bitsize="32" type="uint32"/>

  <reg name="r3" bitsize="32" type="uint32"/>

  <reg name="r4" bitsize="32" type="uint32"/>

  <reg name="r5" bitsize="32" type="uint32"/>

  <reg name="r6" bitsize="32" type="uint32"/>

  <reg name="r7" bitsize="32" type="uint32"/>

  <reg name="r8" bitsize="32" type="uint32"/>

  <reg name="r9" bitsize="32" type="uint32"/>

  <reg name="r10" bitsize="32" type="uint32"/>

  <reg name="r11" bitsize="32" type="uint32"/>

  <reg name="r12" bitsize="32" type="uint32"/>

  <reg name="r13" bitsize="32" type="uint32"/>

  <reg name="r14" bitsize="32" type="uint32"/>

  <reg name="r15" bitsize="32" type="uint32"/>



  <flags id="psw_flags" size="4">

    <field name="C" start="0" end="0"/>

    <field name="Z" start="1" end="1"/>

    <field name="S" start="2" end="2"/>

    <field name="O" start="3" end="3"/>

    <field name="I" start="16" end="16"/>

    <field name="U" start="17" end="17"/>

    <field name="PM" start="20" end="20"/>

    <field name="IPL" start="24" end="27"/>

  </flags>



  <flags id="fpsw_flags" size="4">

    <field name="RM" start="0" end="1"/>

    <field name="CV" start="2" end="2"/>

    <field name="CO" start="3" end="3"/>

    <field name="CZ" start="4" end="4"/>

    <field name="CU" start="5" end="5"/>

    <field name="CX" start="6" end="6"/>

    <field name="CE" start="7" end="7"/>

    <field name="DN" start="8" end="8"/>

    <field name="EV" start="10" end="10"/>

    <field name="EO" start="11" end="11"/>

    <field name="EZ" start="12" end="12"/>

    <field name="EU" start="13" end="13"/>

    <field name="EX" start="14" end="14"/>

    <field name="FV" start="26" end="26"/>

    <field name="FO" start="27" end="27"/>

    <field name="FZ" start="28" end="28"/>

    <field name="FU" start="29" end="29"/>

    <field name="FX" start="30" end="30"/>

    <field name="FS" start="31" end="31"/>

  </flags>



  <reg name="usp" bitsize="32" type="data_ptr"/>

  <reg name="isp" bitsize="32" type="data_ptr"/>

  <reg name="psw" bitsize="32" type="psw_flags"/>

  <reg name="pc" bitsize="32" type="code_ptr"/>

  <reg name="intb" bitsize="32" type="data_ptr"/>

  <reg name="bpsw" bitsize="32" type="psw_flags"/>

  <reg name="bpc" bitsize="32" type="code_ptr"/>

  <reg name="fintv" bitsize="32" type="code_ptr"/>

  <reg name="fpsw" bitsize="32" type="fpsw_flags"/>

  <reg name="acc" bitsize="64" type="uint64"/>

</feature>