Commit 220ad4ca authored by Peter Maydell's avatar Peter Maydell
Browse files

target-arm/translate-a64.c: Remove dead ?: in disas_simd_3same_int() 



In disas_simd_3same_int(), none of the instructions permit is_q
to be false with size == 3 (this would be a vector operation with
a one-element vector, and the instruction set encodes those as
scalar operations). Replace the always-true ?: check with an
assert.

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: default avatarPeter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 1402171881-14343-3-git-send-email-peter.maydell@linaro.org
parent 5661ae6b

target-arm/translate-a64.c

+2 −1
Original line number Diff line number Diff line
@@ -9052,7 +9052,8 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn) 
    }



    if (size == 3) {

        for (pass = 0; pass < (is_q ? 2 : 1); pass++) {

        assert(is_q);

        for (pass = 0; pass < 2; pass++) {

            TCGv_i64 tcg_op1 = tcg_temp_new_i64();

            TCGv_i64 tcg_op2 = tcg_temp_new_i64();

            TCGv_i64 tcg_res = tcg_temp_new_i64();