Commit 21e87c46 authored by Avi Kivity's avatar Avi Kivity Committed by Marcelo Tosatti
Browse files

i386: wire up MSR_IA32_MISC_ENABLE 



It's needed for its default value - bit 0 specifies that "rep movs" is
good enough for memcpy, and Linux may use a slower memcpu if it is not set,
depending on cpu family/model.

Signed-off-by: default avatarAvi Kivity <avi@redhat.com>
Signed-off-by: default avatarMarcelo Tosatti <mtosatti@redhat.com>
parent aa82ba54

target-i386/cpu.h

+5 −0
Original line number Diff line number Diff line
@@ -300,6 +300,10 @@ 


#define MSR_IA32_PERF_STATUS            0x198



#define MSR_IA32_MISC_ENABLE		0x1a0

/* Indicates good rep/movs microcode on some processors: */

#define MSR_IA32_MISC_ENABLE_DEFAULT    1



#define MSR_MTRRphysBase(reg)		(0x200 + 2 * (reg))

#define MSR_MTRRphysMask(reg)		(0x200 + 2 * (reg) + 1)
@@ -691,6 +695,7 @@ typedef struct CPUX86State { 
    uint64_t tsc_deadline;



    uint64_t mcg_status;

    uint64_t msr_ia32_misc_enable;



    /* exception/interrupt handling */

    int error_code;

target-i386/helper.c

+1 −0
Original line number Diff line number Diff line
@@ -98,6 +98,7 @@ void cpu_reset(CPUX86State *env) 
    env->mxcsr = 0x1f80;



    env->pat = 0x0007040600070406ULL;

    env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;



    memset(env->dr, 0, sizeof(env->dr));

    env->dr[6] = DR6_FIXED_1;

target-i386/kvm.c

+15 −0
Original line number Diff line number Diff line
@@ -61,6 +61,7 @@ static bool has_msr_star; 
static bool has_msr_hsave_pa;

static bool has_msr_tsc_deadline;

static bool has_msr_async_pf_en;

static bool has_msr_misc_enable;

static int lm_capable_kernel;



static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
@@ -573,6 +574,10 @@ static int kvm_get_supported_msrs(KVMState *s) 
                    has_msr_tsc_deadline = true;

                    continue;

                }

                if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {

                    has_msr_misc_enable = true;

                    continue;

                }

            }

        }
@@ -889,6 +894,10 @@ static int kvm_put_msrs(CPUState *env, int level) 
    if (has_msr_tsc_deadline) {

        kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSCDEADLINE, env->tsc_deadline);

    }

    if (has_msr_misc_enable) {

        kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE,

                          env->msr_ia32_misc_enable);

    }

#ifdef TARGET_X86_64

    if (lm_capable_kernel) {

        kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
@@ -1138,6 +1147,9 @@ static int kvm_get_msrs(CPUState *env) 
    if (has_msr_tsc_deadline) {

        msrs[n++].index = MSR_IA32_TSCDEADLINE;

    }

    if (has_msr_misc_enable) {

        msrs[n++].index = MSR_IA32_MISC_ENABLE;

    }



    if (!env->tsc_valid) {

        msrs[n++].index = MSR_IA32_TSC;
@@ -1224,6 +1236,9 @@ static int kvm_get_msrs(CPUState *env) 
        case MSR_MCG_CTL:

            env->mcg_ctl = msrs[i].data;

            break;

        case MSR_IA32_MISC_ENABLE:

            env->msr_ia32_misc_enable = msrs[i].data;

            break;

        default:

            if (msrs[i].index >= MSR_MC0_CTL &&

                msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {

target-i386/machine.c

+21 −0
Original line number Diff line number Diff line
@@ -328,6 +328,24 @@ static const VMStateDescription vmstate_msr_tscdeadline = { 
    }

};



static bool misc_enable_needed(void *opaque)

{

    CPUState *env = opaque;



    return env->msr_ia32_misc_enable != MSR_IA32_MISC_ENABLE_DEFAULT;

}



static const VMStateDescription vmstate_msr_ia32_misc_enable = {

    .name = "cpu/msr_ia32_misc_enable",

    .version_id = 1,

    .minimum_version_id = 1,

    .minimum_version_id_old = 1,

    .fields      = (VMStateField []) {

        VMSTATE_UINT64(msr_ia32_misc_enable, CPUState),

        VMSTATE_END_OF_LIST()

    }

};



static const VMStateDescription vmstate_cpu = {

    .name = "cpu",

    .version_id = CPU_SAVE_VERSION,
@@ -441,6 +459,9 @@ static const VMStateDescription vmstate_cpu = { 
        }, {

            .vmsd = &vmstate_msr_tscdeadline,

            .needed = tscdeadline_needed,

        }, {

            .vmsd = &vmstate_msr_ia32_misc_enable,

            .needed = misc_enable_needed,

        } , {

            /* empty */

        }

target-i386/op_helper.c

+6 −0
Original line number Diff line number Diff line
@@ -3280,6 +3280,9 @@ void helper_wrmsr(void) 
    case MSR_TSC_AUX:

        env->tsc_aux = val;

        break;

    case MSR_IA32_MISC_ENABLE:

        env->msr_ia32_misc_enable = val;

        break;

    default:

        if ((uint32_t)ECX >= MSR_MC0_CTL

            && (uint32_t)ECX < MSR_MC0_CTL + (4 * env->mcg_cap & 0xff)) {
@@ -3413,6 +3416,9 @@ void helper_rdmsr(void) 
    case MSR_MCG_STATUS:

        val = env->mcg_status;

        break;

    case MSR_IA32_MISC_ENABLE:

        val = env->msr_ia32_misc_enable;

        break;

    default:

        if ((uint32_t)ECX >= MSR_MC0_CTL

            && (uint32_t)ECX < MSR_MC0_CTL + (4 * env->mcg_cap & 0xff)) {