Loading hw/ide/ahci.c +11 −6 Original line number Diff line number Diff line Loading @@ -386,22 +386,27 @@ static uint64_t ahci_mem_read_32(void *opaque, hwaddr addr) uint32_t val = 0; if (addr < AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR) { switch (addr) { case HOST_CAP: enum AHCIHostReg regnum = addr / 4; assert(regnum < AHCI_HOST_REG__COUNT); switch (regnum) { case AHCI_HOST_REG_CAP: val = s->control_regs.cap; break; case HOST_CTL: case AHCI_HOST_REG_CTL: val = s->control_regs.ghc; break; case HOST_IRQ_STAT: case AHCI_HOST_REG_IRQ_STAT: val = s->control_regs.irqstatus; break; case HOST_PORTS_IMPL: case AHCI_HOST_REG_PORTS_IMPL: val = s->control_regs.impl; break; case HOST_VERSION: case AHCI_HOST_REG_VERSION: val = s->control_regs.version; break; default: break; } } else if ((addr >= AHCI_PORT_REGS_START_ADDR) && (addr < (AHCI_PORT_REGS_START_ADDR + Loading Loading
hw/ide/ahci.c +11 −6 Original line number Diff line number Diff line Loading @@ -386,22 +386,27 @@ static uint64_t ahci_mem_read_32(void *opaque, hwaddr addr) uint32_t val = 0; if (addr < AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR) { switch (addr) { case HOST_CAP: enum AHCIHostReg regnum = addr / 4; assert(regnum < AHCI_HOST_REG__COUNT); switch (regnum) { case AHCI_HOST_REG_CAP: val = s->control_regs.cap; break; case HOST_CTL: case AHCI_HOST_REG_CTL: val = s->control_regs.ghc; break; case HOST_IRQ_STAT: case AHCI_HOST_REG_IRQ_STAT: val = s->control_regs.irqstatus; break; case HOST_PORTS_IMPL: case AHCI_HOST_REG_PORTS_IMPL: val = s->control_regs.impl; break; case HOST_VERSION: case AHCI_HOST_REG_VERSION: val = s->control_regs.version; break; default: break; } } else if ((addr >= AHCI_PORT_REGS_START_ADDR) && (addr < (AHCI_PORT_REGS_START_ADDR + Loading