Commit 211ad3b4 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/sstabellini/tags/xen-20170920-tag' into staging 



Xen 2017/09/20

# gpg: Signature made Thu 21 Sep 2017 03:20:02 BST
# gpg:                using RSA key 0x894F8F4870E1AE90
# gpg: Good signature from "Stefano Stabellini <stefano.stabellini@eu.citrix.com>"
# gpg:                 aka "Stefano Stabellini <sstabellini@kernel.org>"
# Primary key fingerprint: D04E 33AB A51F 67BA 07D3  0AEA 894F 8F48 70E1 AE90

* remotes/sstabellini/tags/xen-20170920-tag:
  xen/pt: allow QEMU to request MSI unmasking at bind time
  xen-disk: use g_new0 to fix build

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents b62b7ed0 a8036336

hw/block/xen_disk.c

+1 −1
Original line number Diff line number Diff line
@@ -1232,7 +1232,7 @@ static int blk_connect(struct XenDevice *xendev) 
        return -1;

    }



    domids = g_malloc0_n(blkdev->nr_ring_ref, sizeof(uint32_t));

    domids = g_new0(uint32_t, blkdev->nr_ring_ref);

    for (i = 0; i < blkdev->nr_ring_ref; i++) {

        domids[i] = blkdev->xendev.dom;

    }

hw/xen/xen_pt.h

+1 −0
Original line number Diff line number Diff line
@@ -180,6 +180,7 @@ typedef struct XenPTMSI { 
    uint32_t addr_hi;  /* guest message upper address */

    uint16_t data;     /* guest message data */

    uint32_t ctrl_offset; /* saved control offset */

    uint32_t mask;     /* guest mask bits */

    int pirq;          /* guest pirq corresponding */

    bool initialized;  /* when guest MSI is initialized */

    bool mapped;       /* when pirq is mapped */

hw/xen/xen_pt_config_init.c

+18 −2
Original line number Diff line number Diff line
@@ -1315,6 +1315,22 @@ static int xen_pt_msgdata_reg_write(XenPCIPassthroughState *s, 
    return 0;

}



static int xen_pt_mask_reg_write(XenPCIPassthroughState *s, XenPTReg *cfg_entry,

                                 uint32_t *val, uint32_t dev_value,

                                 uint32_t valid_mask)

{

    int rc;



    rc = xen_pt_long_reg_write(s, cfg_entry, val, dev_value, valid_mask);

    if (rc) {

        return rc;

    }



    s->msi->mask = *val;



    return 0;

}



/* MSI Capability Structure reg static information table */

static XenPTRegInfo xen_pt_emu_reg_msi[] = {

    /* Next Pointer reg */
@@ -1393,7 +1409,7 @@ static XenPTRegInfo xen_pt_emu_reg_msi[] = { 
        .emu_mask   = 0xFFFFFFFF,

        .init       = xen_pt_mask_reg_init,

        .u.dw.read  = xen_pt_long_reg_read,

        .u.dw.write = xen_pt_long_reg_write,

        .u.dw.write = xen_pt_mask_reg_write,

    },

    /* Mask reg (if PCI_MSI_FLAGS_MASKBIT set, for 64-bit devices) */

    {
@@ -1404,7 +1420,7 @@ static XenPTRegInfo xen_pt_emu_reg_msi[] = { 
        .emu_mask   = 0xFFFFFFFF,

        .init       = xen_pt_mask_reg_init,

        .u.dw.read  = xen_pt_long_reg_read,

        .u.dw.write = xen_pt_long_reg_write,

        .u.dw.write = xen_pt_mask_reg_write,

    },

    /* Pending reg (if PCI_MSI_FLAGS_MASKBIT set, for 32-bit devices) */

    {

hw/xen/xen_pt_msi.c

+10 −3
Original line number Diff line number Diff line
@@ -24,6 +24,7 @@ 
#define XEN_PT_GFLAGS_SHIFT_DM             9

#define XEN_PT_GFLAGSSHIFT_DELIV_MODE     12

#define XEN_PT_GFLAGSSHIFT_TRG_MODE       15

#define XEN_PT_GFLAGSSHIFT_UNMASKED       16



#define latch(fld) latch[PCI_MSIX_ENTRY_##fld / sizeof(uint32_t)]
@@ -155,7 +156,8 @@ static int msi_msix_update(XenPCIPassthroughState *s, 
                           int pirq,

                           bool is_msix,

                           int msix_entry,

                           int *old_pirq)

                           int *old_pirq,

                           bool masked)

{

    PCIDevice *d = &s->dev;

    uint8_t gvec = msi_vector(data);
@@ -171,6 +173,8 @@ static int msi_msix_update(XenPCIPassthroughState *s, 
        table_addr = s->msix->mmio_base_addr;

    }



    gflags |= masked ? 0 : (1u << XEN_PT_GFLAGSSHIFT_UNMASKED);



    rc = xc_domain_update_msi_irq(xen_xc, xen_domid, gvec,

                                  pirq, gflags, table_addr);
@@ -273,8 +277,10 @@ int xen_pt_msi_setup(XenPCIPassthroughState *s) 
int xen_pt_msi_update(XenPCIPassthroughState *s)

{

    XenPTMSI *msi = s->msi;



    /* Current MSI emulation in QEMU only supports 1 vector */

    return msi_msix_update(s, msi_addr64(msi), msi->data, msi->pirq,

                           false, 0, &msi->pirq);

                           false, 0, &msi->pirq, msi->mask & 1);

}



void xen_pt_msi_disable(XenPCIPassthroughState *s)
@@ -355,7 +361,8 @@ static int xen_pt_msix_update_one(XenPCIPassthroughState *s, int entry_nr, 
    }



    rc = msi_msix_update(s, entry->addr, entry->data, pirq, true,

                         entry_nr, &entry->pirq);

                         entry_nr, &entry->pirq,

                         vec_ctrl & PCI_MSIX_ENTRY_CTRL_MASKBIT);



    if (!rc) {

        entry->updated = false;