Commit 20b2323e authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180426' into staging 



target-arm queue:
 * xilinx_spips: Correct SNOOP_NONE state when flushing the txfifo
 * timer/aspeed: fix vmstate version id
 * hw/arm/aspeed_soc: don't use vmstate_register_ram_global for SRAM
 * hw/arm/aspeed: don't make 'boot_rom' region 'nomigrate'
 * hw/arm/highbank: don't make sysram 'nomigrate'
 * hw/arm/raspi: Don't bother setting default_cpu_type
 * PMU emulation: some minor bugfixes and preparation for
   support of other events than just the cycle counter
 * target/arm: Use v7m_stack_read() for reading the frame signature
 * target/arm: Remove stale TODO comment
 * arm: always start from first_cpu when registering loader cpu reset callback
 * device_tree: Increase FDT_MAX_SIZE to 1 MiB

# gpg: Signature made Thu 26 Apr 2018 11:46:31 BST
# gpg:                using RSA key 3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>"
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20180426:
  xilinx_spips: Correct SNOOP_NONE state when flushing the txfifo
  timer/aspeed: fix vmstate version id
  hw/arm/aspeed_soc: don't use vmstate_register_ram_global for SRAM
  hw/arm/aspeed: don't make 'boot_rom' region 'nomigrate'
  hw/arm/highbank: don't make sysram 'nomigrate'
  hw/arm/raspi: Don't bother setting default_cpu_type
  target/arm: Make PMOVSCLR and PMUSERENR 64 bits wide
  target/arm: Fix bitmask for PMCCFILTR writes
  target/arm: Allow EL change hooks to do IO
  target/arm: Add pre-EL change hooks
  target/arm: Support multiple EL change hooks
  target/arm: Fetch GICv3 state directly from CPUARMState
  target/arm: Mask PMU register writes based on PMCR_EL0.N
  target/arm: Treat PMCCNTR as alias of PMCCNTR_EL0
  target/arm: Check PMCNTEN for whether PMCCNTR is enabled
  target/arm: Use v7m_stack_read() for reading the frame signature
  target/arm: Remove stale TODO comment
  arm: always start from first_cpu when registering loader cpu reset callback
  device_tree: Increase FDT_MAX_SIZE to 1 MiB

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 569df5b6 fbf32752

device_tree.c

+1 −1
Original line number Diff line number Diff line
@@ -29,7 +29,7 @@ 


#include <libfdt.h>



#define FDT_MAX_SIZE  0x10000

#define FDT_MAX_SIZE  0x100000



void *create_device_tree(int *sizep)

{

hw/arm/aspeed.c

+1 −1
Original line number Diff line number Diff line
@@ -225,7 +225,7 @@ static void aspeed_board_init(MachineState *machine, 
         * SoC and 128MB for the AST2500 SoC, which is twice as big as

         * needed by the flash modules of the Aspeed machines.

         */

        memory_region_init_rom_nomigrate(boot_rom, OBJECT(bmc), "aspeed.boot_rom",

        memory_region_init_rom(boot_rom, OBJECT(bmc), "aspeed.boot_rom",

                               fl->size, &error_abort);

        memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR,

                                    boot_rom);

hw/arm/aspeed_soc.c

+1 −2
Original line number Diff line number Diff line
@@ -186,13 +186,12 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) 
    }



    /* SRAM */

    memory_region_init_ram_nomigrate(&s->sram, OBJECT(dev), "aspeed.sram",

    memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram",

                           sc->info->sram_size, &err);

    if (err) {

        error_propagate(errp, err);

        return;

    }

    vmstate_register_ram_global(&s->sram);

    memory_region_add_subregion(get_system_memory(), ASPEED_SOC_SRAM_BASE,

                                &s->sram);

hw/arm/boot.c

+1 −1
Original line number Diff line number Diff line
@@ -1188,7 +1188,7 @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) 
     * actually loading a kernel, the handler is also responsible for

     * arranging that we start it correctly.

     */

    for (cs = CPU(cpu); cs; cs = CPU_NEXT(cs)) {

    for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {

        qemu_register_reset(do_cpu_reset, ARM_CPU(cs));

    }

}

hw/arm/highbank.c

+1 −1
Original line number Diff line number Diff line
@@ -291,7 +291,7 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id) 
    memory_region_add_subregion(sysmem, 0, dram);



    sysram = g_new(MemoryRegion, 1);

    memory_region_init_ram_nomigrate(sysram, NULL, "highbank.sysram", 0x8000,

    memory_region_init_ram(sysram, NULL, "highbank.sysram", 0x8000,

                           &error_fatal);

    memory_region_add_subregion(sysmem, 0xfff88000, sysram);

    if (bios_name != NULL) {