Commit 1e6c50ad authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-5.1-20200720' into staging 



ppc patch queue 20200720

Here are some assorted fixes for qemu-5.1:
 * SLOF update with improved TPM handling, and fix for possible stack
   overflows on many-vcpu machines
 * Fix for NUMA distances on NVLink2 attached GPU memory nodes
 * Fixes to fail more gracefully on attempting to plug unsupported PCI bridge types
 * Don't allow pnv-psi device to be user created

# gpg: Signature made Mon 20 Jul 2020 06:29:21 BST
# gpg:                using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392
# gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" [full]
# gpg:                 aka "David Gibson (Red Hat) <dgibson@redhat.com>" [full]
# gpg:                 aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" [full]
# gpg:                 aka "David Gibson (kernel.org) <dwg@kernel.org>" [unknown]
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E  87DC 6C38 CACA 20D9 B392

* remotes/dgibson/tags/ppc-for-5.1-20200720:
  pseries: Update SLOF firmware image
  spapr: Add a new level of NUMA for GPUs
  spapr_pci: Robustify support of PCI bridges
  ppc/pnv: Make PSI device types not user creatable

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 873ec69a b25fbd6a

hw/ppc/pnv_psi.c

+1 −0
Original line number Diff line number Diff line
@@ -929,6 +929,7 @@ static void pnv_psi_class_init(ObjectClass *klass, void *data) 
    dc->desc = "PowerNV PSI Controller";

    device_class_set_props(dc, pnv_psi_properties);

    dc->reset = pnv_psi_reset;

    dc->user_creatable = false;

}



static const TypeInfo pnv_psi_info = {

hw/ppc/spapr.c

+19 −2
Original line number Diff line number Diff line
@@ -890,10 +890,16 @@ static int spapr_dt_rng(void *fdt) 
static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt)

{

    MachineState *ms = MACHINE(spapr);

    SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms);

    int rtas;

    GString *hypertas = g_string_sized_new(256);

    GString *qemu_hypertas = g_string_sized_new(256);

    uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) };

    uint32_t refpoints[] = {

        cpu_to_be32(0x4),

        cpu_to_be32(0x4),

        cpu_to_be32(0x2),

    };

    uint32_t nr_refpoints = ARRAY_SIZE(refpoints);

    uint64_t max_device_addr = MACHINE(spapr)->device_memory->base +

        memory_region_size(&MACHINE(spapr)->device_memory->mr);

    uint32_t lrdr_capacity[] = {
@@ -945,8 +951,12 @@ static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt) 
                     qemu_hypertas->str, qemu_hypertas->len));

    g_string_free(qemu_hypertas, TRUE);



    if (smc->pre_5_1_assoc_refpoints) {

        nr_refpoints = 2;

    }



    _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points",

                     refpoints, sizeof(refpoints)));

                     refpoints, nr_refpoints * sizeof(refpoints[0])));



    _FDT(fdt_setprop(fdt, rtas, "ibm,max-associativity-domains",

                     maxdomains, sizeof(maxdomains)));
@@ -4584,9 +4594,16 @@ DEFINE_SPAPR_MACHINE(5_1, "5.1", true); 
 */

static void spapr_machine_5_0_class_options(MachineClass *mc)

{

    SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);

    static GlobalProperty compat[] = {

        { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-5.1-associativity", "on" },

    };



    spapr_machine_5_1_class_options(mc);

    compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len);

    compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));

    mc->numa_mem_supported = true;

    smc->pre_5_1_assoc_refpoints = true;

}



DEFINE_SPAPR_MACHINE(5_0, "5.0", false);

hw/ppc/spapr_pci.c

+56 −0
Original line number Diff line number Diff line
@@ -1480,6 +1480,57 @@ static void spapr_pci_bridge_plug(SpaprPhbState *phb, 
    add_drcs(phb, bus);

}



/* Returns non-zero if the value of "chassis_nr" is already in use */

static int check_chassis_nr(Object *obj, void *opaque)

{

    int new_chassis_nr =

        object_property_get_uint(opaque, "chassis_nr", &error_abort);

    int chassis_nr =

        object_property_get_uint(obj, "chassis_nr", NULL);



    if (!object_dynamic_cast(obj, TYPE_PCI_BRIDGE)) {

        return 0;

    }



    /* Skip unsupported bridge types */

    if (!chassis_nr) {

        return 0;

    }



    /* Skip self */

    if (obj == opaque) {

        return 0;

    }



    return chassis_nr == new_chassis_nr;

}



static bool bridge_has_valid_chassis_nr(Object *bridge, Error **errp)

{

    int chassis_nr =

        object_property_get_uint(bridge, "chassis_nr", NULL);



    /*

     * slotid_cap_init() already ensures that "chassis_nr" isn't null for

     * standard PCI bridges, so this really tells if "chassis_nr" is present

     * or not.

     */

    if (!chassis_nr) {

        error_setg(errp, "PCI Bridge lacks a \"chassis_nr\" property");

        error_append_hint(errp, "Try -device pci-bridge instead.\n");

        return false;

    }



    /* We want unique values for "chassis_nr" */

    if (object_child_foreach_recursive(object_get_root(), check_chassis_nr,

                                       bridge)) {

        error_setg(errp, "Bridge chassis %d already in use", chassis_nr);

        return false;

    }



    return true;

}



static void spapr_pci_plug(HotplugHandler *plug_handler,

                           DeviceState *plugged_dev, Error **errp)

{
@@ -1508,6 +1559,9 @@ static void spapr_pci_plug(HotplugHandler *plug_handler, 
    g_assert(drc);



    if (pc->is_bridge) {

        if (!bridge_has_valid_chassis_nr(OBJECT(plugged_dev), errp)) {

            return;

        }

        spapr_pci_bridge_plug(phb, PCI_BRIDGE(plugged_dev));

    }
@@ -2035,6 +2089,8 @@ static Property spapr_phb_properties[] = { 
                     pcie_ecs, true),

    DEFINE_PROP_UINT64("gpa", SpaprPhbState, nv2_gpa_win_addr, 0),

    DEFINE_PROP_UINT64("atsd", SpaprPhbState, nv2_atsd_win_addr, 0),

    DEFINE_PROP_BOOL("pre-5.1-associativity", SpaprPhbState,

                     pre_5_1_assoc, false),

    DEFINE_PROP_END_OF_LIST(),

};

hw/ppc/spapr_pci_nvlink2.c

+10 −3
Original line number Diff line number Diff line
@@ -362,9 +362,9 @@ void spapr_phb_nvgpu_ram_populate_dt(SpaprPhbState *sphb, void *fdt) 
                                                    &error_abort);

        uint32_t associativity[] = {

            cpu_to_be32(0x4),

            SPAPR_GPU_NUMA_ID,

            SPAPR_GPU_NUMA_ID,

            SPAPR_GPU_NUMA_ID,

            cpu_to_be32(nvslot->numa_id),

            cpu_to_be32(nvslot->numa_id),

            cpu_to_be32(nvslot->numa_id),

            cpu_to_be32(nvslot->numa_id)

        };

        uint64_t size = object_property_get_uint(nv_mrobj, "size", NULL);
@@ -375,6 +375,13 @@ void spapr_phb_nvgpu_ram_populate_dt(SpaprPhbState *sphb, void *fdt) 
        _FDT(off);

        _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));

        _FDT((fdt_setprop(fdt, off, "reg", mem_reg, sizeof(mem_reg))));



        if (sphb->pre_5_1_assoc) {

            associativity[1] = SPAPR_GPU_NUMA_ID;

            associativity[2] = SPAPR_GPU_NUMA_ID;

            associativity[3] = SPAPR_GPU_NUMA_ID;

        }



        _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity,

                          sizeof(associativity))));

include/hw/pci-host/spapr.h

+1 −0
Original line number Diff line number Diff line
@@ -94,6 +94,7 @@ struct SpaprPhbState { 
    hwaddr nv2_gpa_win_addr;

    hwaddr nv2_atsd_win_addr;

    SpaprPhbPciNvGpuConfig *nvgpus;

    bool pre_5_1_assoc;

};



#define SPAPR_PCI_MEM_WIN_BUS_OFFSET 0x80000000ULL