Commit 1db8b5ef authored by Peter Crosthwaite's avatar Peter Crosthwaite Committed by Peter Maydell
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cadence_uart: Flush queued characters on reset 



Reset can be used to empty the rx-fifo. As the fifo full condition is
used to return false from can_receive, queued rx data should be flushed
on reset accordingly.

Cc: Wendy Liang <jliang@xilinx.com>
Cc: Jason Wu <huanyu@xilinx.com>

Signed-off-by: default avatarPeter Crosthwaite <peter.crosthwaite@xilinx.com>
Reported-by: default avatarJason Wu <huanyu@xilinx.com>
Message-id: 494c1e005e225c915d295ddfd75d992ad2dabc3c.1364964526.git.peter.crosthwaite@xilinx.com
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent fd7f8a99

hw/cadence_uart.c

+1 −0
Original line number Diff line number Diff line
@@ -157,6 +157,7 @@ static void uart_rx_reset(UartState *s) 
{

    s->rx_wpos = 0;

    s->rx_count = 0;

    qemu_chr_accept_input(s->chr);



    s->r[R_SR] |= UART_SR_INTR_REMPTY;

    s->r[R_SR] &= ~UART_SR_INTR_RFUL;