Commit 1da85c2a authored by Greg Kurz's avatar Greg Kurz Committed by David Gibson
Browse files

spapr_pci: Define SPAPR_MAX_PHBS in hw/pci-host/spapr.h 



PHB hotplug will bring more users for it. Let's define it along with
the PHB defines from which it is derived for simplicity.

While here fix a misleading comment about manual placement, which was
abandoned with 30b3bc5a.

Signed-off-by: default avatarGreg Kurz <groug@kaod.org>
Reviewed-by: default avatarCédric Le Goater <clg@kaod.org>
Signed-off-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
parent c13ee169

hw/ppc/spapr.c

+0 −2
Original line number Diff line number Diff line
@@ -3840,8 +3840,6 @@ static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index, 
     * 1TiB 64-bit MMIO windows for each PHB.

     */

    const uint64_t base_buid = 0x800000020000000ULL;

#define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \

                        SPAPR_PCI_MEM64_WIN_SIZE - 1)

    int i;



    /* Sanity check natural alignments */

include/hw/pci-host/spapr.h

+4 −2
Original line number Diff line number Diff line
@@ -94,11 +94,13 @@ struct sPAPRPHBState { 
    ((1ULL << 32) - SPAPR_PCI_MEM_WIN_BUS_OFFSET)

#define SPAPR_PCI_MEM64_WIN_SIZE     0x10000000000ULL /* 1 TiB */



/* Without manual configuration, all PCI outbound windows will be

 * within this range */

/* All PCI outbound windows will be within this range */

#define SPAPR_PCI_BASE               (1ULL << 45) /* 32 TiB */

#define SPAPR_PCI_LIMIT              (1ULL << 46) /* 64 TiB */



#define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \

                        SPAPR_PCI_MEM64_WIN_SIZE - 1)



#define SPAPR_PCI_2_7_MMIO_WIN_SIZE  0xf80000000

#define SPAPR_PCI_IO_WIN_SIZE        0x10000