Commit 1d725ae9 authored by Maciej W. Rozycki's avatar Maciej W. Rozycki Committed by Leon Alrae
Browse files

target-mips: Also apply the CP0.Status mask to MTTC0 



Make CP0.Status writes made with the MTTC0 instruction respect this
register's mask just like all the other places.  Also preserve the
current values of masked out bits.

Signed-off-by: default avatarMaciej W. Rozycki <macro@codesourcery.com>
Reviewed-by: default avatarLeon Alrae <leon.alrae@imgtec.com>
Signed-off-by: default avatarLeon Alrae <leon.alrae@imgtec.com>
parent cbb26c9a

target-mips/op_helper.c

+2 −1
Original line number Diff line number Diff line
@@ -1413,9 +1413,10 @@ void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1) 
void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1)

{

    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    uint32_t mask = env->CP0_Status_rw_bitmask & ~0xf1000018;

    CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);



    other->CP0_Status = arg1 & ~0xf1000018;

    other->CP0_Status = (other->CP0_Status & ~mask) | (arg1 & mask);

    sync_c0_status(env, other, other_tc);

}